This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family. We determined an appropriate technology-dependent power factor Kp to calculate the power consumption on Virtex-chips, and developed a special benchmark test design to conduct our investigations. Additionally, the derived formulas are evaluated on two typical industrial designs. Our own emulation environments called SPYDER-ASIC-X1 and SPYDER-VIRTEX-X2 were used, which are best suited for the emulation of hardware designs for embedded systems.

This paper presents the emulation of an embedded system with hard real-time constraints and response times of about 220 /spl mu/s. We show that for such fast reactive systems, the software overhead of a real time operating system becomes a limiting factor. We analyze the influence of novel microcontroller features, e.g., different on-chip caches, which tend to accelerate execution, but make it less predictable. These investigations have been conducted using our own emulation environment called SPYDER-CORE-P1.

This paper presents the emulation of an embedded system with hard real time constraints and response times of about 220~s.We show that for such fast reactive systems, the software overhead of a Real Time Operating System (RTOS) becomes a limiting factor, consuming up to 77% of the total execution performance.We analyze features of different FPGA architectures in order to solve the system performance bottleneck.We show that moving functionality from software to hardware through exploiting the fine grained on-chip SRAM capability of the Xilinx XC4000 architecture, that feature eliminates the RTOS overhead by only a slight increase of about 28% of the used FPGA CLB resources.These investigations have been conducted using our own emulation environment called SPYDER-CORE-Pl.

Novel FPGA architectures combined with new implementation methods influence the widespread area of embedded system design. Current research results based on the Global Run Time Reconfiguration (RTR) method show improvements to the functional density of up to 500% in contrast to the widely used Compile Time Reconfiguration (CTR) method. In addition, the RTR method applied to a partial reconfigurable architecture, like Xilinx XC6000, promises further enhancements. This paper analyses different implementation methods in order to exploit the resources of specific FPGA architectures. The development of an ATM diagnostic monitor serves as a realistic application to analyse these methods. We will analyse the differences between the XC4000E/EX and XC6000 FPGA architecture, based on their use of the same CTR implementation method. Additionally: applying Local RTR to XC6000 leads to a further benefit of about 20% in contrast to the CTR method. The evaluation process is based on the FZI internal rapid prototyping environment, which is best suited for sophisticated ATM applications.

No abstract available.