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Yoshihiro Tohma

dblp:58/6482 · DBLP profile ↗
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18ranked-venue papers
12as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 9 · 6 first-authorSystems, architecture and hardware · 8 · 5 first-authorApplied, interdisciplinary, general and emerging computing · 3 · 2 first-authorSecurity and privacy · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
3 papers
Software testing · 100%
Computer architecture, parallel and distributed computing, and storage systems
8 papers
Hardware reliability and fault tolerance · 69% Electronic design automation · 28% Integrated circuit design · 4%

Topics — the 13 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software testing
software reliability
0.031991
The Estimation of Parameters of the Hypergeometric Distribution and Its Application to the Software Reliability Growth Model · IEEE Trans. Software Eng. 1991
Parameter Value Computation by Least Square Method and Evaluation of Software Availability and Reliability at Service-Operation by the Hyper-Geometric Distribution Software Reliability Growth Model (HGDM) · ICSE 1991
Structural Approach to the Estimation of the Number of Residual Software Faults Based on the Hyper-Geometric Distribution · IEEE Trans. Software Eng. 1989
Software testing › software reliability › software reliability modeling
software reliability growth model
0.031991
The Estimation of Parameters of the Hypergeometric Distribution and Its Application to the Software Reliability Growth Model · IEEE Trans. Software Eng. 1991
Parameter Value Computation by Least Square Method and Evaluation of Software Availability and Reliability at Service-Operation by the Hyper-Geometric Distribution Software Reliability Growth Model (HGDM) · ICSE 1991
Structural Approach to the Estimation of the Number of Residual Software Faults Based on the Hyper-Geometric Distribution · IEEE Trans. Software Eng. 1989
Hardware reliability and fault tolerance
neural network fault tolerance
0.011996
Fault-Tolerant Design of Neural Networks for Solving Optimization Problems · IEEE Trans. Computers 1996
Electronic design automation
logic synthesis
0.041979
Universal Multicode STT State Assignments for Asynchronous Sequential Machines · IEEE Trans. Computers 1979
On Universal Single Transition Time Asynchronous State Assignments · IEEE Trans. Computers 1978
A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974
Electronic design automation › logic synthesis › state assignment
asynchronous sequential machine state assignment
0.021979
Universal Multicode STT State Assignments for Asynchronous Sequential Machines · IEEE Trans. Computers 1979
On Universal Single Transition Time Asynchronous State Assignments · IEEE Trans. Computers 1978
Hardware reliability and fault tolerance › self-checking circuits
fail-safe sequential machine
0.021974
Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory · IEEE Trans. Computers 1974
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code · IEEE Trans. Computers 1971
Integrated circuit design › digital circuit design › sequential circuit design
asynchronous sequential circuits
0.011974
A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974
Hardware reliability and fault tolerance › design for reliability
fail-safe circuit design
0.011974
A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974
Electronic design automation › logic synthesis
state assignment
0.011974
A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits · IEEE Trans. Computers 1974
Hardware reliability and fault tolerance › fault-tolerant architecture
fault-tolerant sequential machine
0.011971
Failure-Tolerant Sequential Machines with Past Information · IEEE Trans. Computers 1971
Electronic design automation › logic synthesis
boolean function decomposition
0.011964
Decompositions of Logical Functions Using Majority Decision Elements · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design › sequential circuit design
flip-flop
0.011974
Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory · IEEE Trans. Computers 1974
Coding theory
error-correcting codes
0.011971
Failure-Tolerant Sequential Machines with Past Information · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

triplication · 0.0merging function · 0.0least-squares sum method · 0.0least squares · 0.0hyper-geometric distribution · 0.0segmentation · 0.0composite estimation · 0.0tracey's method · 0.0separating systems · 0.0ordered partition · 0.0binary code vector assignment · 0.0karnaugh map · 0.0
YearPublicationVenuePosition
2003 Dependability Issue on Autonomic Computing Environment
Yoshihiro Tohma
ISORC1
2002 Fault Tolerance in Autonomic Computing Environment
abstract
Since the characteristic of current information systems is the dynamic change of their configurations and scales with non-stop provision of their services, the system management should inevitably rely on autonomic computing. Since fault tolerance is one of the important system management issues, it should also be incorporated in an autonomic computing environment. This paper argues what should be taken into consideration and what approach could be available to realize the fault tolerance in such environments.
Yoshihiro Tohma
PRDC1
1996 Fault-Tolerant Design of Neural Networks for Solving Optimization Problems
abstract
First, the incorporation of the alternative ways of representing the solution to the traveling salesman problem by neural network is proposed to deal with the asymmetric tolerance of neural networks to unidirectional faults. Next, in order to cope with the simultaneous occurrence of a s-a-0 and s-a-1 faults, the triplication scheme with a proper merging function is considered. Finally, the combination of the alternative representations and the triplication scheme is used.
Yoshihiro Tohma, Yoichi Koyanagi
IEEE Trans. Computers1
1995 Parameter estimation of hyper-geometric distribution software reliability growth model by genetic algorithms
abstract
Usually, parameters in software reliability growth models are not known, and they must be estimated by using observed failure data. Several estimation methods have been proposed, but most of them have restrictions such as the existence of derivatives on evaluation functions. On the other hand, genetic algorithms (GA) provide us with robust optimization methods in many fields. We apply GA to the parameter estimation of the hyper-geometric distribution software reliability growth model. Experimental result shows that GA is effective in the parameter estimation and removes restrictions from software reliability growth models.
Takashi Minohara, Yoshihiro Tohma
ISSRE2
1991 Parameter Value Computation by Least Square Method and Evaluation of Software Availability and Reliability at Service-Operation by the Hyper-Geometric Distribution Software Reliability Growth Model (HGDM)
Raymond Jacoby, Yoshihiro Tohma
ICSE2
1991 Parameter estimation of the hyper-geometric distribution model for real test/debug data
abstract
The hyper-geometric distribution model (HGDM) has been proposed for estimating the number of faults initially resident in a program at the beginning of the test/debug process. However, the parameters of the hyper-geometric distribution necessary for making the estimation were previously determined by the 3-dimensional exhaustive search and therefore, much time was needed to get the numerical result. The authors demonstrate, using real test/debug data of programs, that the least square sum method can be well applied to the estimation of such parameters of the hyper-geometric distribution model. Thus, the time needed for calculating the estimates can be reduced greatly.>
Yoshihiro Tohma, Hisashi Yamano, Morio Ohba, Raymond Jacoby
ISSRE1
1991 The Estimation of Parameters of the Hypergeometric Distribution and Its Application to the Software Reliability Growth Model
abstract
Six ways to estimate parameters of the hypergeometric distribution are investigated, and their accuracies are examined comparatively. It is demonstrated that the least-squares sum method is the best one among those tried, and can be applied to real test/debug data for estimating the number of faults still resident in a program after test/debugging. By this method the estimation time can be reduced greatly.>
Yoshihiro Tohma, Hisashi Yamano, Morio Ohba, Raymond Jacoby
IEEE Trans. Software Eng.1
1990 The hyper-geometric distribution software reliability growth model (HGDM): precise formulation and applicability
abstract
The hyper-geometric distribution is used to estimate the number of initial faults residual in software at the beginning of the test-and-debug phase. The hyper-geometric distribution growth model (HGD model) is well suited to making estimates for the observed growth curves of the accumulated number of detected faults. The advantage of the proposed model is the applicability to all kinds of observed data. By application of a single model, exponential growth curves as well as S-shaped growth curves can be estimated. The precise formulation of the HGD model is presented. The exact relationship of this model to the NHPP Goel-Okumoto growth model and the delayed S-shaped growth model is shown. With the introduction of a variable fault detection rate, the goodness of fit of the estimated growth curve to the growth curve of real observed faults is increased significantly. Different examples of the applicability of the model to real observed data are presented.>
Raymond Jacoby, Yoshihiro Tohma
COMPSAC2
1989 Models to estimate the number of faults still resident in the software after test/debug process
abstract
Models used to estimate the number of residual software faults are examined. The models were developed by universities and industries in Japan. It has been shown that the hypergeometric distribution model can be applied to real data of different types. The relationship between the model based on the hypergeometric distribution and those based on the nonhomogeneous Poisson process has been revealed.>
Yoshihiro Tohma
COMPSAC1
1989 Hyper-geometric distribution model to estimate the number of residual software faults
abstract
It is shown that the hyper-geometric distribution model can be applied to different types of test-and-debug data to estimate the number of initial software faults. Examples show that the fitness of the estimated growth curves of the model to real data is satisfactory. The relationship of the model to those proposed earlier is clarified. Some of them can be expressed as a special case of the proposed model. The S-shaped characteristic of the growth curve can also be introduced using this model.>
Yoshihiro Tohma, Raymond Jacoby, Yukihisa Murata, Moriki Yamamoto
COMPSAC1
1989 Structural Approach to the Estimation of the Number of Residual Software Faults Based on the Hyper-Geometric Distribution
abstract
Models based on the hyper-geometric distribution for estimating the number of residual software faults are proposed. The application of the basic model shows that its fit to real data is good. Two ways of improving the model, using a segmentation technique and composite estimation, respectively, are shown. The segmentation technique appears quite effective, particularly when the growth curve of the cumulative number of detected faults bends sharply. The applications of these models to real data are demonstrated.>
Yoshihiro Tohma, Kenshin Tokunaga, Shinji Nagase, Yukihisa Murata
IEEE Trans. Software Eng.1
1979 Universal Multicode STT State Assignments for Asynchronous Sequential Machines
abstract
A universal single transition time (STT) state assignment is a way to give a valid STT state assignment in which all state variables that must change in a given transition are allowed to change simultaneously without critical races for any asynchronous sequential machine regardless of the configuration of its flow table. This paper presents a new systematic procedure for constructing universal STT state assignments and shows that the procedure can give better upper bounds on the number of state variables required for realizing asynchronous normal flow tables than any known universal STT state assignments, although there is some difference in standpoint between earlier works and the present one. It is further shown that the procedure can also be applied to improve the best known bounds for (2, 1) separating systems which are known to be less restricted universal assignments. The feature of the procedure lies in the idea that two binary code vectors are assigned to each internal state. In the resulting universal STT assignments, the number of state variables required is given by 2 · m1.59 where m = [log2 n], n being the number of states and [X] being the least integer ≥ X. Furthermore, the resulting (2, 1) separating systems require 2 ·m state variables.
Takashi Nanya, Yoshihiro Tohma
IEEE Trans. Computers2
1978 On Universal Single Transition Time Asynchronous State Assignments
abstract
One of two constructive procedures for universal single transition time (STT) state assignments presented in the paper [1] by Friedman et al. is not correct. A correct constructive procedure can be obtained by simply modifying the procedure of the literature with an additional restriction.
Takashi Nanya, Yoshihiro Tohma
IEEE Trans. Computers2
1974 A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits
abstract
The problem of the realization of fail-safe asynchronous sequential circuits was recently studied by Patterson and Sawin. This correspondence presents a different approach to the same subject which, in some cases, yield us simpler realization than those by the methods ever proposed, combining the notion of the ordered partition with Tracey's method for the state assignment of asynchronous sequential circuit.
Y. Mukai, Yoshihiro Tohma
IEEE Trans. Computers2
1974 Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory
abstract
A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.
Yoshihiro Tohma
IEEE Trans. Computers1
1971 Failure-Tolerant Sequential Machines with Past Information
abstract
A sequential machine must have certain redundant information in order to be capable of correcting error. As past inputs and past states are redundant, a sequential machine with error correction capability is constructable by making use of these elements of past information. This paper describes conditions of state assignments, numbers of required redundant state variables, and estimation of reliability of failure-tolerant sequential machines.
Yoshihiro Tohma, Susumu Aoyagi
IEEE Trans. Computers1
1971 Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
abstract
A fail-safe sequential machine is one that produces safe-side output when failures occur in the machine. This paper presents a new method of realization of fail-safe sequential machines under the following assumptions: 1) failure is caused by a single fault of element in the machine, 2) output of faulty element is stuck at one or zero, and 3) input does not malfunction.
Yoshihiro Tohma, Yasuyoshi Ohyama, Ryozo Sakai
IEEE Trans. Computers1
1964 Decompositions of Logical Functions Using Majority Decision Elements
abstract
A method of decomposing logical functions using three input majority gates is given. This method requires that at least one of the inputs to the gate be specified, and from this the other inputs may be found. For unate functions one of the variables may be completely separated at each level. A method using a Karnaugh map is proposed for finding the best function to use as the specified input, which will make the other inputs to the majority gate easier to synthesize.
Yoshihiro Tohma
IEEE Trans. Electron. Comput.1