The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture highly scalable in that L and P can be chosen to optimize performance for particular problems and reconfigurable in that, once L and P are fixed, problems of any size can still be mapped onto the architecture. The authors demonstrate techniques and methods for mapping computational structures to the architecture by considering the case of the 1-D butterfly network (1DBN). Since many other computational structures can be mapped to 1DBN, this gives a firm application base for the architecture. The authors also demonstrate methods for scheduling and controlling the memory system.>

A high-performance partitionable parallel/pipeline architecture (P/sup 3/A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P/sup 3/A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining.>

A theoretical study which allows determination of the minimum number of vias for realizable multilayer channel routing under a topological model is presented. The theory is sufficiently general to solve a variety of problems under different technological constraints, e.g. VLSI multilayer switchbox and channel routing, through-hole printed circuit board (PCB) channels, and single-layer routing. Topological routing is concerned with wire intersection but not area, zero-width wires and zero-area vias being assumed. Unconstrained via minimization (UVM) is not constrained to a prerouted topology. This paper presents restrictive cases of UVM, finding most to be NP-hard, but the case resulting from constraints of traditional switchbox or channel routing to be solvable in O(kn/sup 2/), where k is the maximum number of pins of a net layer and n is the number of pins. The minimum number of vias for various switchbox and channel routing benchmarks are reported.>