The rapid development of artificial intelligence-of-things (AIOT) has led to a significant increase in intelligent nodes, presenting substantial challenges to internode communication. Semantic communication systems based on artificial neural networks (ANNs) have demonstrated greater robustness than traditional Shannon systems. However, the significant resource overhead makes hardware implementation challenging, and the low efficiency of information compression places considerable strain on communication bandwidth. This work proposed a hybrid semantic system that employs ANNs for high-precision semantic extraction at the server and spiking neural networks (SNNs) for high-performance information compression in the spatiotemporal dimension and semantic comprehending with low-hardware cost at the edge. A hardware-friendly, event-based neuromorphic core has been developed with low-hardware resource consumption and a high sampling rate for SNN deployment. The evaluation results indicate that the hybrid semantic system reduces the bandwidth by 95.8%, while maintaining a high sampling rate of 1000 Sa/s, outperforming traditional systems. Meanwhile, it enables a low entropy of the receiving end after four samples. Considering both bandwidth overhead and the entropy of the receiving end, the hybrid system achieves a high information compression ratio (ICR), surpassing the ANN-based system over 20 times. This work is expected to reveal the significance of neuromorphic computing in enabling high-performance information compression and transmission (Tx) in semantic communication.

This paper presents a novel 8-to-12 b, 1-to-20 MSPS Reconfigurable SAR ADC for low power multi-standard systems to avoid multi-ADCs’ integration in SoC designs thus reducing power and area. To enhance power efficiency across varying conversion rates and resolutions, proposed ADC integrates a custom-designed source-degeneration dynamic comparator along with a reconfigurable asynchronous mechanism. Furthermore, to broaden its applicability, the ADC utilizes an optimized window-switching (OWS) scheme to mitigate dynamic and static performance degradation stemming from capacitor array nonlinearity without the need for additional calibration algorithms. The prototype is designed in 40nm CMOS process with 1.2 V supply and occupied an active area of 0.0445mm2. Post-simulation results show that ADC’s 8b 1MSPS mode achieves SNDR of 48.86 dB, SFDR of 64.49 dB and FoMWof 154.5 fJ/conv-step. And 10b 5MSPS achieves SNDR of 60.89 dB, SFDR of 74.23 dB and FoMWof 45.8 fJ/conv-step. 12b 20MSPS achieves SNDR of 70.33 dB, SFDR of 83.59 dB and FoMWof 16.4 fJ/conv-step.

The transformer model has demonstrated significant capabilities in various intelligent tasks, attracting widespread attention in recent years. However, it involves numerous complex operations, including large-bit-width multiplication, division, matrix transposition, and exponentiation. These require substantial storage and computational resources, making it challenging to deploy on edge devices. This work introduces a neuromorphic transformer architecture with low hardware cost for AI edge computing (AI-EC). At the structural level, it absorbs scaling factors within the self-attention mechanism into weight matrixes, thereby eliminating the division caused by the scaling operation. Additionally, a transposition calculation method is proposed to perform matrix transposition using dedicated memory access strategies and optimized data flow designs, which reduces logic resource overhead and avoids memory access discontinuities. At the computing paradigm level, the architecture employs spike-driven computing, substituting multi-bit multipliers with AND logic for synaptic operations. The paradigm introduces high sparsity to computational data, which is effectively exploited to reduce the computational workload of the architecture. The results indicate that the architecture successfully eliminates high-cost operators and significantly reduces computational expenses. Eventually, this architecture is verified as a prototype using a 28 nm CMOS process library, demonstrating a compact logic area of sub-0.2 mm2and a high energy efficiency of 0.34 pJ/SOP @ 50MHz. This work is expected to promote the application of transformers in edge computing and the development of intelligent edge applications.

Edge devices require low power consumption and compact area, which poses challenges for visual signal processing. This work introduces an energy-efficient heterogeneous neuromorphic system-on-chip (SoC) for edge visual computing. The neuromorphic core design incorporates advanced technologies, such as sparse-aware synaptic calculation, partial membrane potential update, non-uniform weight quantization, and partial parallel computing, achieving excellent energy efficiency, computing performance, and area utilization. Twenty neuromorphic cores and twelve multi-mode connected-matrix-based routers form a network-on-chip (NoC) with fullerene-like topology. Its average degree of communication nodes exceeds traditional topologies by 32 % and maintains a minimum degree variance of 0.93, thereby enabling advanced decentralized on-chip communication. Moreover, the NoC can be scaled up through extended off-chip high-level router nodes. At the top layer of the SoC, a RISC-V CPU and a 20-core neuromorphic processor are tightly coupled to form a heterogeneous architecture. Eventually, the chip is fabricated within a 3.41 mm2die area under 55 nm CMOS technology, achieving a low power density of 0.52 mW/mm2and a high neuron density of 30.23 K/mm2. Its effectiveness is verified across different visual tasks, with a best energy efficiency of 0.96 pJ/SOP. This work is expected to promote the development of neuromorphic computing in edge visual applications.

This paper presents a novel adaptive common-mode Cancellation Biopotential Amplifier for portable ECG recording. The amplifier features a converge-free adaptive common-mode cancellation (ACMC) loop with nine MOSFETs, two capacitors, two pseudo resistances and one unity gain buffer. Through periodic detecting and compensating common charge induced by common-mode interference (CMI), ACMC circuit is able to suppressed amplitude of CMI over 100x without requiring a convergence process or additional common-mode references. To verify the design, a prototype is fabricated in 0.18μm CMOS process with a 1.8 V supply. Under power consumption of 16.7μW, measurement results show that 20VPPCMI with a frequency range spanning from 20Hz to 80Hz is suppressed below 200mVPPthat guarantees the normal operation of subsequent instrument amplifier. Also, the input-referred noise (IRN) within 100Hz and common-mode rejection ratio at 50Hz are 1.26μVrmsand 91dB, respectively.

Edge-AI computing requires high energy efficiency, low power consumption, and relatively high flexibility and compact area, challenging the AI-chip design. This work presents a 0.96 pJ/SOP heterogeneous neuromorphic system-on-chip (SoC) with fullerene-like interconnection topology for edge-AI computing. The neuromorphic core integrates different technologies to augment computing energy efficiency, including sparse computing, partial membrane potential updates, and non-uniform weight quantization. Multiple neuromorphic cores and multi-mode routers form a fullerene-like network-on-chip (NoC). The average degree of communication nodes exceeds traditional topologies by 32%, with a minimal degree variance of 0.93, allowing advanced decentralized on-chip communication. Additionally, the NoC can be scaled up through extended off-chip high-level router nodes. A RISC-V CPU and a neuromorphic processor are tightly coupled and fabricated within a 5.42 mm2die area under 55 nm CMOS technology. The chip has a low power density of 0.52 mW/mm2, reducing 67.5% compared to related works, and achieves a high neuron density of 30.23 K/mm2. Eventually, the chip is demonstrated to be effective on different datasets and achieves 0.96 pJ/SOP energy efficiency.

This paper presents a subthreshold-leakage-current-based fully CMOS temperature-to-digital converter with high accuracy and supply rejection. The subthreshold current ratio is constructed by different channel lengths of the same MOSFET type, providing high accuracy and less corner dependence. In addition, the supply sensitivity is enhanced by the proposed subthreshold-leakage-current-based sensing element (SE) and the frequency ratio of two identical currents to frequency converters (CFCs). The prototype was implemented in a 180nm CMOS process. It achieves an inaccuracy of ±0.8°C ($3\sigma$) from 0°C to 100°C after two-point calibration with a resolution of 120mK. Over a wide supply range from 0.8V to 1.6V, the temperature sensor shows a supply sensitivity of 0.9°/V at 30°C. Over the temperature range of 0–100°C, the power supply sensitivity is smaller than 3.4°C/V. Operating at 1V, the sensor has a power consumption of 20nW at 30°C, leading to an FoM of 14.4 pJ$\cdot \text{K}^{2}$.

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62-$\mu \text{W}$power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively.

This article presents a low-power code-recombination (CR) analog-to-digital converter (ADC) with generic feature extraction for wearable electrocardiogram (ECG) sensors in wireless body sensor network (WBSN) applications. The CR ADC features a search forward procedure (SFP) and a search backward procedure (SBP) to hunt for part of the quantization steps cutting down bitcycle and power consumption. Also, CR ADC outputs a digital stream named$K$data served as a compressed feature. A prototyped chip including a proposed ADC is fabricated in a 0.13-$\mu \text{m}$CMOS process. With a 0.6-V supply voltage and a 10-kS/s sampling rate, the measured signal-to-noise-distortion range (SNDR) and spurious-free dynamic range (SFDR) are 58.34 and 70.2 dB, respectively. The ADC consumes only 40-nW power when input residue is within the prediction range defined by ADC’s resolution and the reference voltage, achieving a figure-of-merit (FoM) of 6.2 fJ/conversion-step. The data$K$occupy 2/5 of the raw data and are conducted to categorize cardiovascular diseases illustrating at least 96% accuracy.

A VCO-based(Voltage Controlled Oscillator) temperature sensor with multi-threshold MOSFET based sensing element is proposed. The proposed temperature sensor converts temperature variation into frequency and then into digital readings. In the proposed temperature sensor, the ratio of two reference currents, generated by P-MOSFETs operated in sub-threshold region and with different channel doping concentration, is used to sense the variation of temperature and achieves a 3σ inaccuracy of ±0.06°C after first-order poly-fit with systematic nonlinearity removal. The ratio of currents is then transformed into difference of the output frequencies of two identical CMOS-thyristor based VCOs, both of which are optimized to alleviate the impact of charge sharing and charge injection on the precision of the temperature sensor. In this way, there is no need for generating an external reference clock. The prototype is fabricated in a 130nm CMOS process and achieves an inaccuracy of +0.44°C/-0.4°C. The proposed sensor achieves a resolution of 0.1°C and a resolution FoM of 0.12nJ·K2. The prototype occupies an area of 0.07mm2.

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes 59.9 μW of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

This paper presents a novel energy efficient code-recombination analog-to-digital converter (ADC) for low power applications. Dynamic tracking algorithm, search forward procedure (SFP) and search backward procedure (SBP) are introduced in this manuscript. Also, to generate the test voltage sequence fed in comparator, a binary code factor (BCF) is presented. And a lookup table (LUT) for digitizing the output code is employed. To verify the algorithm, a 10-bit ADC is designed in 0.13μm CMOS process with a 0.6 V supply. Given a 41.5 Hz sinusoid signal, the proposed ADC exhibits 9.75 effective number of bit (ENOB) and 80.9dB spur-free dynamic range (SFDR) at 10k Hz sample rate. Given full-scale sinusoid signals whose frequency are under 160Hz, the ADC achieves 39-77.4nW power consumption with 2.19-10.8 bitcycles in average, respectively. Also, simulation result shows the DNL and INL is bounded at 0.117 and 0.245LSBs.

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2 MS/s SAR ADC is designed using 130nm CMOS process with 0.5 V power supply voltage. Simulation results shows the ADC achieve signal-to-noise distortion ratio (SNDR) of 59.63 dB, corresponding to an effective number of bits (ENOB) of 9.61 bits and consumes 3.2 µW, resulting in a figure of merit (FOM) of 2.06 fJ/c-s.

This paper proposes a low-power and area efficient 14-bit Successive Approximation Register (SAR) analog-to-digital converter (ADC) for array sensors. A hybrid capacitor digital-to-analog converter (CDAC), which consist of a 10-bit split CDAC and a 5-bit serial CDAC, is utilized to increase the area efficiency. The total required number of unit capacitors are only 52. A foreground digital calibration is employed to compensate the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The HSPICE post-layout simulation results show that the peak DNL and INL of the proposed ADC are enhanced from 1.27/-1 LSB and 17.29/-16.24 LSB to 0.74/-0.49 LSB and 1.27/-0.54 LSB, respectively. And ENOB is improved from 9.82bit to 13.65 bit at 48.14-KHz input after calibration. With a power consumption of 59 μW, the FOM is 45.42 fJ/step. The CDAC occupies an active area of 15 × 800 μm2and the area efficiency ADC core is only 0.934 μm2/code.

A fully integrated supply voltage and temperature variation-tolerant relaxation oscillator for biomedical systems has been presented. Concepts of dynamic threshold and switched resistors are proposed to improve the frequency stability against power supply and temperature variations, respectively. This design was verified in a 0.35-$\mu{\rm m}$standard CMOS process with a 3 V supply. Measurement results show the frequency drift of 0.6% from 2.4 to 4.0 V and temperature stability of 53.9 ppm/$^{\circ}{\rm C}$as temperature varied from${-}{30}{}^{\circ}{\rm C}$to 120$^{\circ}{\rm C}$at a typical working frequency of 4 MHz. With the consideration of resistor and transistor matching, the oscillator was implemented in a core area of 0.05${\rm mm}^{2}$.

This paper presents a 10-bit subrange successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FOM) is 34.2fJ/conversion-step.