Power and area efficiency of time-encoded neural networks make them highly suitable for smart portable applications. The main limitation here is the high sensitivity against circuit impairments like mismatch effects or PVT variations, which are usually mitigated by means of calibration circuitry. The purpose of this manuscript is to propose a novel time-encoded unit for Artificial Neural Networks, and make an in-depth analysis on how these effects degrade the accuracy in classification tasks. As an application example, image recognition tasks are selected using MNIST dataset. It is checked that the proposed unit does not require calibration to compensate mismatch effects, can be implemented with small devices, and shows accuracy degradation due to PVT variations that can be overcome with simple calibration or by increasing the number of bits used for the inputs and outputs of the unit. With a very simple neural network structure, 94.1 %-accuracy is achieved with a worst case simulated TOPS/W value of 24, and an area of 0.039 mm2in a 65 nm CMOS design node, with a data representation of 5 bits in the inputs and outputs of the unit and 4 bits used for the weights.

The focus of this paper is to demonstrate first that high order noise shaped data converters can be digitally generated in open loop architectures, avoiding both stability problems and complex analog loops, and second that a low power PLL design can be used as the clock generator for such VCO-based ADCs. An open-loop 2nd-order VCO-based ADC is proposed by means of a digital approximation of the pulse shaping filter to a second-order sinc function. The pulse shaping filter is digitized with a time reference signal used to quantize time differences and taken from a low power PLL implemented on silicon using a 65nm CMOS design node. The proposed architecture is firstly described theoretically and afterwards is experimentally tested for an audio bandwidth application. A model of the PLL output phase noise is measured in the test chip and is used in a simulation platform to check the real performance that could be experimentally achieved. The results prove that the time reference requirements can be met with low power architectures, achieving negligible SNR degradation and opening up the possibility of implementing scalable, low power and small area all-digital Nth-order VCO-based ADCs.

In this manuscript, we propose a time-domain, mostly digital band-pass filter architecture for audio signal feature extraction. The filter is composed of a single voltagecontrolled-oscillator (VCO) as signal encoder and monostables generating digital pulses at the edges of the pulse frequency modulated VCO output. The band-pass filtering phenomena are observed when we combine these digital pulses with different lengths, and its functionality is proved by the behavioral simulations performed with a circuit proposal built in MATLAB/Simulink. Compared to other state-of-the-art solutions, our filter architecture can take the benefit from advancement of digital technology nodes and design tools thanks to its mostly digital implementation. Moreover, the band-pass filter possesses friendly programmability, whose center frequency can be easily tuned by modifying the digital pulse length, and the single VCO encoder promises an easy calibration circuit. Finally, a recurrent neural network is trained and tested based on the features extracted from this architecture, the excellent speech/non-speech hitting rate shows the feasibility of our band-pass filters for voice activity tasks.

A multi-stage, open-loop Current Controlled Oscillator (CCO)-based Analog-to-Digital Converter (ADC) is proposed for non-linearity compensation and enhanced noise shaping. This architecture consists of multiple CCO-based stages connected in a cascading manner. The digital outputs of these stages are skillfully combined through digital filters to both compensate for the distortion of the CCOs and increase the noise shaping order. We present an application example with three stages, demonstrating a significant reduction in distortion, particularly from the first stage, and a notable improvement in Signal-to-Noise and Distortion Ratio (SNDR) performance when compared to first-order structures.

A voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.

This work proposes a robust-against-blockers radio receiver structure using a Nyquist voltage-controlled oscillator-based Analog-to-Digital converter (VCO-based ADC). The approach consists of customizing a pulse shaping filter, placing nulls at the frequencies where some blockers are expected. The frequency response of the filter is approximated by digital quantization with lookup tables (LUTs), which enables high programmability for multiband signal reception. The proposed structure is compared to the conventional oversampled one, showing significant power reduction with similar resolution performance.

A ring-oscillator based circuit is proposed for features extraction tasks within smart speech recognition and voice activity detectors applications. The architecture performs all the operations needed for conventional features extraction but making use of only time-encoded based circuits in the analog domain. This results in a compact and simple structure, easily scalable and suitable for the deepest CMOS nodes leading for ultra-low and small solutions. The proposal is described theoretically and functionally checked with behavioral simulations in MATLAB. Additionally, the filtering stage is designed in a 65-nm process and validated with transient simulations providing promising results referring estimated power and area.

This work introduces a new VCO-ADC architecture. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We show in this paper that the oscillator frequency of such configuration reacts to the product of the two inputs. Therefore, the ring oscillator can be used both as a mixer and to digitally acquire the lowpass converted component. A first system-level approach is made to optimize the distortion by a proper number of taps in the ring oscillator. To confirm the system level predictions, some circuit simulations have been made. As a result, it is observed that VCO non-linearity limits the SNDR in a similar way as in conventional low pass VCOADCs. In a 65nm CMOS process, 55 dB of SNDR is achieved in a 5-MHz bandwidth for a 1 MHz downconverted signal, using a sampling clock of 2.5 GHz and input signals centered in 70 MHz and 71 MHz.

The main limitation of voltage-controlled oscillator based analog-to-digital converters (VCO-ADC) is the VCO non-linear voltage-to-frequency response, especially with ring-oscillators. This issue strongly restricts the final resolution we are able to get from the converter. In addition, flicker noise is a limitation for low-bandwidth applications. We propose a novel way of compensating both the VCO non-linearity and the phase noise effects. By means of a time varying switched-capacitor circuit, we build a purely analog compensation loop where jitter clock and DAC non-linearity do not suppose a limitation. The loop is closed with an opamp that provides gain to the compensation operation. The idea is proposed theoretically and tested by simulations, showing a good performance for audio or sensing applications.

The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that links continuous time sigma delta modulators of an arbitrary order with Pulse Frequency Modulators. This novel point of view also predicts the spectral contents of a sigma delta encoded sequence beyond the white quantization noise model. The quantization noise can be split in two components, a deterministic one representing the carrier harmonic sidebands of a Pulse Frequency Encoded signal and a noise shaped pseudorandom signal representing the sampling operation. We seize these findings to propose a conjecture on the stability of a sigma delta modulator.

This work describes a systematic way to implement a band-pass noise-transfer-function (NTF) in an analog-to-digital converter implemented with a voltage-controlled-oscillator (VCO-ADC). The approach is based on the pulse frequency modulation (PFM) interpretation of a VCO-ADC, where the NTF is defined by a suitable pulse shaping filter inserted after the VCO. In this work, we explain how this pulse shaping filter can be defined to implement a quadrature band-pass NTF. In addition to describing the best theoretical way to achieve this, we also propose a hardware implementation using a digital delay line whose outputs are decoded with two lookup tables (LUTs). This enables tuning the NTF in software. Transient simulations were made to validate the implementation and robustness of the proposed approach and a case study of the power consumption was made for the case of a 65-nm CMOS process. Due to the mostly digital circuit implementation, the proposed structure is suitable for even newer ultra deep submicron CMOS processes.

This paper shows how to enhance the resolution of a VCO based ADC by transforming a ring oscillator into a continuous-time maximum length sequence generator. The code spreading provided by the maximum length sequence can be decoded after sampling by a look up table. Compared to an M tap ring oscillator, an equivalent maximum length sequence generator enhances the resolution of the resulting ADC by a factor 2M/M. We derive the basic system analysis for this new ADC architecture and show a simulation example.

A theoretical approach to the problem of replicating continuous-time systems with frequency modulated oscillators is proposed. It has been shown that continuous time filters and especially, the loop filter of a sigma-delta modulator, can be implemented with VCOs and digital circuitry. The analysis of these architectures is usually based on the integral relationship between frequency and phase in an oscillator. However, the spectrum of a modulated oscillator contains components at the harmonics of the oscillation frequency that cannot be easily described using the phase-frequency relationship. We propose a model in which a VCO is considered a signal encoder instead of an integrator. This model is applied then to the design of a band pass-sigma delta modulator.

The analytical formulation of the output DFT of an oversampled converter based on a VCO has been recently disclosed for the single-bit case. However, most practical VCO-ADCs are constructed with a multibit configuration using a multiphase ring oscillator architecture. This paper shows that the spectral properties of a single-bit VCO-ADC are retained in the multibit case if an equivalent model is employed. This means that similar equations used to study the performance of single-bit ring oscillator can also be applied to the multibit case. Also, a multibit PFM-ADC has been proposed as an alternative to a conventional VCO-ADC, showing differences in the output spectrum respect to the VCO-ADCs based on ring oscillators. This paper describes these differences and how to apply the previous equations to study the PFM-ADC architecture.

Oversampled ADCs based on voltage-controlled oscillators have been analyzed using statistical models inherited from sigma-delta modulation. This letter shows that the discrete Fourier transform of a VCO-ADC output sequence can be calculated analytically for single tone inputs. The calculation is based on the transformation of the VCO output into a pulse frequency modulated signal that can be represented by a trigonometric series. Knowledge of the VCO-ADC output spectrum allows accurate evaluation of the SNDR dependence with the VCO oscillation frequency and gain constant. The SNDR predictions of the proposed model have been compared to behavioral simulations displaying only a deviation of 0.7 dB.