This paper presents the bit error rate (BER) performance validation of digital baseband communication systems on a field-programmable gate array (FPGA). The proposed BER tester (BERT) integrates fundamental baseband signal processing modules of a typical wireless communication system along with a realistic fading channel simulator and an accurate Gaussian noise generator onto a single FPGA to provide an accelerated and repeatable test environment in a laboratory setting. Using a developed graphical user interface, the error rate performance of single- and multiple-antenna systems over a wide range of parameters can be rapidly evaluated. The FPGA-based BERT should reduce the need for time-consuming software-based simulations, hence increasing the productivity. This FPGA-based solution is significantly more cost effective than conventional performance measurements made using expensive commercially available test equipment and channel simulators.

The accurate simulation of wireless channels is important since it permits the realistic and repeatable performance measurement of wireless systems. A new technique is proposed for simulating Rayleigh fading channels with isotropic or non-isotropic scattering and with arbitrary temporal correlation. Fading samples are generated by passing Gaussian samples through a spectrum shaping filter. A new iterative algorithm is then presented for designing stable complex infinite impulse response (IIR) filters with quantised coefficients. The algorithm utilises a least-squares cost function augmented with a barrier function to ensure filter stability and to reduce quantisation noise. The performance of the proposed filter design algorithm is verified with 18-bit fixed-point simulations of different fading channel scenarios including isotropic and non-isotropic scattering and the IEEE 802.11n model F fading spectrum.

This brief presents an improved layered space-time symbol detection algorithm for multiple-input multiple-output (MIMO) wireless systems. The proposed detection scheme utilises a different layer-ordering strategy than the so-called optimal ordering used in the conventional Bell Laboratories Layered Space-Time (BLAST) algorithm. To calculate the nulling vectors and their associated ordering, instead of using direct numerical techniques, the authors utilise a numerically stable iterative solution. It is shown that the performance of the proposed detector approaches closely that of an optimal maximum-likelihood detector at the expense of greater computational complexity compared with BLAST. Utilising the proposed parameterisable detector, one can trade off between the computational requirement and the error-rate performance.

An efficient implementation of Nakagami-mand Weibull variate generators on a single field-programmable gate array (FPGA) is presented. The hardware model first generates a correlated Rayleigh fading variate sequence and then transforms it into a sequence of Nakagami-mor Weibull fading variates. A biquad processor facilitates the compact implementation of a Rayleigh variate generator with arbitrary autocorrelation properties. A combination of logarithmic and linear domain segmentations along with piece-wise linear approximations is used to accurately implement the nonlinear numerical functions required to transform the correlated Rayleigh fading process into Nakagami-m or Weibull fading processes. When implemented on a Xilinx Virtex-5 5VSX240TFF1738-2 FPGA, the fading simulator uses only 1.6% of the configurable slices, 1.2% of the DSP48E modules and 3 block memories, while operating at 120 MHz, generating 120 million complex variates per second. The throughput can be increased up to 373 MHz with this FPGA if two separate clock sources are utilized.

This article presents an ultra-compact and high-throughput reconfigurable fading channel simulator that supports a relatively large number of propagation paths. To closely reflect actual radio channels, the authors used a recently improved Rayleigh and Ricean fading channel model based on the sum-of-sinusoids technique. The improved model is optimised for hardware compactness. To achieve a fast fading variate generation rate with much less hardware and no significant loss in accuracy, the new scheme first generates fading samples at a lower rate using a time-multiplexed datapath that can be fit into a small fraction of a field-programmable gate array (FPGA). In the second step, the simulator uses a compact multiplication-free linear interpolator to produce the fading samples at the full symbol rate. Implementing a 64-path fading channel simulator on a Xilinx Virtex-4 XC4VLX200-11 FPGA requires only 13 044 (14%) of the configurable slices, 10 (2%) of the block memories and one (1%) of the dedicated DSP blocks, while generating 64 × 191 million complex-valued fading samples per second. The simulated paths can be readily combined to form high path count models for multiple-input multiple-output systems as well as frequency-selective channels.

The authors propose a compact and fast fading channel simulator for the baseband verification and prototyping of multiple-input multiple-output (MIMO) wireless communication systems. The simulator accurately and efficiently implements models of both single-bounce and multiple-bounce geometric propagation conditions. Fading samples are generated at a low rate, comparable to the Doppler frequency, and then interpolated to match the desired sample rate. Bit-true simulations verify the accuracy of the hardware simulator. As an example, when implemented on a Xilinx XC5VLX110 field-programmable gate array (FPGA), the 4×4 MIMO geometric fading channel simulator occupies only 6.6% of the configurable slices while generating more than 16×324 million samples per second. The geometric MIMO fading channel simulator is well suited for use in an FPGA-based error rate performance verification system.

Compact and fast implementations of digital Rayleigh and Ricean variate generators are presented. Polynomial curve fitting is utilized along with a combination of logarithmic and uniform domain segmentation to provide accuracy, compactness and fast variate generation. A typical instantiation of the proposed Rayleigh generator occupies 124 (<;1%) of the configurable slices, two dedicated multipliers (<;1%), and one on-chip block memory (<; 1%) of a Xilinx Virtex-5 field-programmable gate array (FPGA) and operates at 317 MHz, generating 317 million Rayleigh variates per second. The Ricean variate generator implementation on the same device utilizes 366 (<; 1%) of the logical slices, three on-chip block memories ( <;1%), and 11 (2.8%) of the dedicated multipliers. The application of the Rayleigh and Ricean variate generators is demonstrated in a FPGA-based bit error rate simulator that measures at hardware speeds the symbol error rate performance of a typical wireless communication system over Rayleigh and Ricean fading channels.

This paper presents a unified architecture for the compact implementation of several key elementary functions, including reciprocal, square root, and logarithm, in single-precision floating-point arithmetic. The proposed high-throughput design is based on uniform domain segmentation and curve fitting techniques. Numerically accurate least-squares regression is utilized to calculate the polynomial coefficients. The architecture is optimized by analyzing the trade-off between the size of the required memory and the precision of intermediate variables to achieve the minimum 23-bit accuracy required for single-precision floating-point representation. The efficiency of the proposed unified data path is demonstrated on a common field-programmable gate array.

The design of communication systems becomes increasingly challenging as product complexity and cost pressures increase and as the time-to-market is shortened more than ever before. This paper presents a bit error rate tester (BERT) for the hardware-based verification of the physical layer (PHY) layer of emerging wireless systems. We integrate fundamental modules of a typical PHY layer along with the channel simulator onto a single field-programmable gate array (FPGA). For a proof-of-concept, we present the results of a FPGA-based performance verification exercise for a multiple antenna system. The proposed BERT system significantly decreases the test time compared to conventional software-based verification, hence increasing designer productivity.

Many emerging communication technologies significantly increase the complexity of the physical layer and have dramatically increased the number of operating configurations. To ensure maximum performance, designers have to optimize their algorithm implementations, which requires for comprehensive performance testing in all possible operating modes various channel conditions. This paper presents a flexible and affordable framework for baseband algorithm development and performance verification for digital communication systems with an arbitrary number of modules, each operating at a possibly different sampling rate with various latencies. The proposed architecture is scalable to support complex scenarios, such as multiple antenna systems, and is compact enough to be implemented within a single field-programmable gate array.

Emulation of fading channels is a key step in the design and verification of wireless communication systems. Testing wireless transceivers with actual fading channels is inconvenient due to unrepeatable and uncontrollable channel conditions. In this paper we present a compact field-programmable gate array (FPGA) implementation for a circuit that generates temporally-correlated fading variates for emulating multipath fading radio channels. The implemented fading emulator is flexible enough to model different propagation scenarios accurately and is compact enough that it can be implemented on the same FPGA with the design under test (DUT) for greater emulation efficiency and speed-up. Several streams of Rayleigh or Rician fading variates are generated by passing independent samples of Gaussian noise through spectrum shaping filters. The new baseband emulator is fully parameterizable and can emulate a wide variety of single and multiple antenna scenarios.

This article describes a significantly improved sum-of-sinusoids-based model for the accurate simulation of time-correlated Rayleigh and Rician fading channels. The proposed model utilises random walk processes instead of random variables for some of the sinusoid parameters to more accurately reproduce the behaviour of wireless radio propagation. Every fading block generated using our model has accurate statistical properties on its own and hence, unlike previously proposed models, there is no need for time-consuming ensemble-averaging over multiple blocks. Using numerical simulation it is shown that the important statistical properties of the generated fading samples have excellent agreement with the theoretical reference functions. A fixed-point hardware implementation of the corresponding Rayleigh and Rician fading channel simulator on a field-programmable gate array (FPGA) is presented. By efficiently scheduling the operations, the reconfigurable fading channel simulator is compact enough that it can be efficiently used to simulate multipath scenarios and multiple-antenna systems (e.g. a 4×4 MIMO channel) using a single FPGA.

We present a fading model with a compact and fast hardware implementation suitable for correlated Rayleigh fading channel simulators. The proposed scheme is based on the sum-of-sinusoids model because of its flexibility and efficient mapping onto hardware. Using numerical simulation, it is shown that the statistical properties of the generated fading variates match the theoretical reference model. Since the cross-correlations between sequences of generated fading variates are small, this model can also be used to implement a time-correlated multiple-input multiple-output (MIMO) fading channel simulator on a single field-programmable gate array (FPGA). The MIMO channel simulator can also be extended to support spatial correlation between generated fading samples. An implementation of a spatiotemporally correlated (4, 4) MIMO channel simulator on a Xilinx Virtex-II Pro XC2VP100-6 FPGA uses 46% of the configurable slices, 30% of the dedicated multipliers, and 32% of the on-chip block memories while generating 4 times 201 million 2 times 16-bit complex-valued fading samples per second.

Most commonly-used pseudo-random number generators (PNGs) in computer systems are based on linear recurrence. These deterministic PNGs have fast and compact implementations, andean ensure very long periods. However, the points generated by linear PNGs in fact have a regular lattice structure and are thus not suit able for applications that rely on the assumption of uniformly distributed pseudo-random numbers (PNs). In this paper we propose and evaluate several fast and compact linear, non-linear, and hybrid PNGs for a field- programmable gate array (FPGA). The PNGs have excellent equidistribution properties and very small autocorrelations, and have very long repetition periods. The distribution and long-range correlation properties of the new generators are efficiently, and much more rapidly, estimated at hardware speeds using designed modules within the FPGA. The results of these statistical tests confirm that the combination of several linear PNGs or the combination of even one small non-linear PNG with a linear PNG significantly improves the statistical properties of the generated PNs.

We present an accurate model for compact implementations of Rayleigh and Rician fading channels. Verification of the proposed fading simulator is performed by comparing the simulated statistics with those of the ideal reference models. A parameterizable field-programmable gate array (FPGA) implementation of the channel simulator is presented. The design is readily scalable to support multipath fading channels and multiple-input multiple-output (MIMO) systems. A 16-path fading channel, providing either Rician or Rayleigh fading, uses 41% of the configurable slices, 33% of the dedicated multipliers, and 32% of the on-chip block memories of a Xilinx Virtex-II Pro XC2VP100-6 FPGA while generating over 200 million complex- valued fading coefficients per second.

We present a flexible architecture for evaluating the bit-error-rate (BER) performance of prototype digital baseband communication systems. Using an efficient elastic buffer interface, an arbitrary baseband module can be added to the cascaded architecture of a digital baseband communication system, independent of the module's operating rate, its position in the cascade structure, and its latency. The proposed BER tester uses an accurate fading channel model and a Gaussian noise generator to provide a realistic and repeatable test environment in the laboratory. This evaluation environment should reduce the need for time-consuming field tests, hence reducing the time-to-market and increasing productivity.

A stochastic sum-of-sinusoids based simulation model is proposed for Rayleigh and Rician fading channels. The time-averaged statistical properties of the new model have been significantly improved compared to existing models. Verification of the proposed fading simulator is carried out by comparing its measured statistical properties with the properties of the ideal reference models. The simulator utilizes a time-overlapped implementation strategy to provide a compact design suitable for multiple antenna simulators. An implementation of the resulting Rician fading simulator on a Xilinx Virtex-II Pro XC2VP100- 6 FPGA uses only 2% of the configurable slices, 1% of the dedicated multipliers, and 2% of the on-chip block memories while generating 201 million 2 times 16-bit complex-valued fading samples per second. The scalable design of the fading channel simulator enables a straightforward implementation of multiple antenna channels and different diversity schemes.

A compact, fast, and accurate realization of a digital Gaussian variate generator (GVG) based on the Box-Muller algorithm is presented. The proposed GVG has a faster Gaussian sample generation rate and higher tail accuracy with a lower hardware cost than published designs. The GVG design can be readily configured to achieve arbitrary tail accuracy (i.e., with a proposed 16-bit datapath up to plusmn15 times the standard deviation sigma) with only small variations in hardware utilization, and without degrading the output sample rate. Polynomial curve fitting is utilized along with a hybrid (i.e., combination of logarithmic and uniform) segmentation and a scaling scheme to maintain accuracy. A typical instantiation of the proposed GVG occupies only 534 configurable slices, two on-chip block memories, and three dedicated multipliers of the Xilinx Virtex-II XC2V4000-6 field-programmable gate array (FPGA) and operates at 248 MHz, generating 496 million Gaussian variates (GVs) per second within a range of plusmn6.66sigma. To accurately achieve a range of plusmn9.4sigma, the GVG uses 852 configurable slices, three block memories, and three on-chip dedicated multipliers of the same FPGA while still operating at 248 MHz, generating 496 million GVs per second. The core area and performance of a GVG implemented in a 90-nm CMOS technology are also given. The statistical characteristics of the GVG are evaluated and confirmed using multiple standard statistical goodness-of-fit tests.

This paper presents a computationally-efficient design and implementation technique for fading channel simulators. Our fixed-point implementation of a Rayleigh fading channel simulator on a field-programmable gate array (FPGA) utilizes only 4% of the configurable slices, 19% of the dedicated multipliers, and 2% of the on-chip memory blocks, while generating 12.5 million statistically accurate fading variates per second. The designed channel emulator can be parameterized to simulate a wide variety of different channel characteristics over bandwidths of up to 12.5 MHz. The compact simulator can also be instantiated multiple times to assess the performance of communication systems over multiple-input multiple-output (MIMO) channels.

A flexible and compact general-purpose filter processor is presented. This processor is intended for the hardware-based simulation of wireless channels on field-programmable gate arrays (FPGAs). When implemented on a Xilinx Virtex2P XC2VP100-6 FPGA, it utilizes 2% of the configurable slices, 9% of the dedicated 18times18-bitmultipliers, and 14 BlockRAMs. When paired with multiplicationfree interpolators, it can generate up to 300 million fading samples per second. The statistical properties of generated fading samples are shown to closely match the theoretical reference statistical properties.

A fast and compact implementation of nonlinear pseudo-random number generators (PNGs) on a field-programmable gate array (FPGA) is presented. The distribution and correlation properties of PNGs are efficiently, and very rapidly, estimated within the FPGA. It is shown that the pseudo-random output of nonlinear PNGs have significantly improved randomness properties compared to linear PNGs. To the best of our knowledge, this paper presents the first long-range correlation and distribution measurements in hardware for PNGs on FPGAs.

We describe an improved scheme for simulating Rayleigh fading channels which accurately reproduces the required channel statistics. The new scheme is based on the sum- of-sinusoids Rayleigh fading model because of its flexibility and efficient mapping onto hardware. Using numerical simulation it is shown that the statistical properties of the generated fading variates, such as the probability density function, the autocorrelation, and the level crossing rate, follow the desired theoretical properties. A fixed-point implementation of the fading channel simulator on a field-programmable gate array utilizes only 5% of the configurable slices and generates over 200 million 16-bit fading variates per second.