This review aims to analyze the recent literature to find how the preattentive visual process is currently used in information visualization, particularly to improve the cognitive process in chart comprehension (i.e., perceptual effectiveness). The purpose of our literature review is to provide an overview of how concepts related to the preattentive process are used pragmatically in recent research. We searched different bibliography sources between 2010 and 2021, getting 29 articles that fit the review focus. In general, we discovered that the research work on exploiting the preattentive process in information visualization is currently not thoroughly explored. The main contribution of the paper is the analysis of the papers, from which we identified two categories of research directions according to the primary uses of preattentive concepts: “preattentive attributes as design components,” and “the preattentive process as a measuring tool,” with a gap between these two approaches. The review also highlighted two limitations in the current research literature: most works tend to focus on a particular chart type, only, with difficult to generalize results, and the manipulation of preattentive attributes is done implicitly, without providing to the graph designer the suitable awareness over the design decisions impact. We finally present a proposal about how to use the knowledge about the preattentive process in the first stages of design in information visualization to start closing the gap mentioned above with the graph designer.

Nowadays, end users can exploit end-user development (EUD) platforms to personalise their Internet of Things (IoT) ecosystems, typically through trigger–action rules. Unfortunately, within such platforms, users are forced to adopt a unique, vendor-centric abstraction: to define triggers and actions, they must specifically refer to every single device or online service needed to execute the intended behaviours. As a consequence, little social and practical benefits of EUD in this domain have emerged so far. In this paper, we build on the idea that other abstractions besides the vendor-centric one are possible, and that the growth of end-user personalisation in the IoT may depend on their identification. Specifically, we report on the results of a 1-week-long diary study during which 24 participants were free to collect trigger–action rules arising during their daily activities. First, we demonstrate that users would adopt different abstractions by personalising devices, information and people-related behaviours, where the individual is at the centre of the interaction. Then, we show that the adopted abstraction may depend on different factors, ranging from the user profile, e.g. their programming experience, to the context in which the personalisation is introduced. While users are inclined to personalise physical objects in the home, for example, they often go ‘beyond devices’ in the city, where they are more interested in the underlying information. Finally, we discuss the retrieved results by identifying new design opportunities to improve the relationship between users and the IoT.

Several tools have been developed to support novices learning to program. Most of them focus on the code and provide features regarding the visualization of the data structures or the debugging. However, in introductory programming courses, students are typically given exercises in the form of a problem written in natural language; and the first challenge they face is understanding the problem, identifying the relevant information, and then translating that information into code. To our knowledge, little attention has been paid to proposing tools targeted at supporting this problem-solving step, even though it is crucial for deriving a correct solution. In this paper, we present an IDE to encourage novices to understand the problem before start coding, decompose it down into subproblems, explore alternative implementations for each subproblem, and arrange these implementations to build a general solution. Finally, the adopted problem-solving approach is discussed.

In the Internet of Things era, users are willing to personalize the joint behavior of their connected entities, i.e., smart devices and online service, by means of trigger-action rules such as “IF the entrance Nest security camera detects a movement, THEN blink the Philips Hue lamp in the kitchen.” Unfortunately, the spread of new supported technologies makes the number of possible combinations between triggers and actions continuously growing, thus motivating the need of assisting users in discovering new rules and functionality, e.g., through recommendation techniques. To this end, we present , a semantic Conversational Search and Recommendation (CSR) system able to suggest pertinent IF-THEN rules that can be easily deployed in different contexts starting from an abstract user’s need. By exploiting a conversational agent, the user can communicate her current personalization intention by specifying a set of functionality at a high level, e.g., to decrease the temperature of a room when she left it. Stemming from this input, implements a semantic recommendation process that takes into account ( a ) the current user’s intention , ( b ) the connected entities owned by the user, and ( c ) the user’s long-term preferences revealed by her profile. If not satisfied with the suggestions, then the user can converse with the system to provide further feedback, i.e., a short-term preference , thus allowing to provide refined recommendations that better align with the original intention. We evaluate by running different offline experiments with simulated users and real-world data. First, we test the recommendation process in different configurations, and we show that recommendation accuracy and similarity with target items increase as the interaction between the algorithm and the user proceeds. Then, we compare with other similar baseline recommender systems. Results are promising and demonstrate the effectiveness of in recommending IF-THEN rules that satisfy the current personalization intention of the user.

In the Internet of Things era, users are willing to personalize the joint behavior of their connected entities, i.e., smart devices and online service, by means of IF-THEN rules. Unfortunately, how to make such a personalization effective and appreciated is still largely unknown. On the one hand, contemporary platforms to compose IF-THEN rules adopt representation models that strongly depend on the exploited technologies, thus making end-user personalization a complex task. On the other hand, the usage of technology-independent rules envisioned by recent studies opens up new questions, and the identification of available connected entities able to execute abstract users' needs become crucial. To this end, we present HeyTAP, a conversational and semantic-powered trigger-action programming platform able to map abstract users' needs to executable IF-THEN rules. By interacting with a conversational agent, the user communicates her personalization intentions and preferences. User's inputs, along with contextual and semantic information related to the available connected entities, are then used to recommend a set of IF-THEN rules that satisfies the user's needs. An exploratory study on 8 end users preliminary confirms the effectiveness and the appreciation of the approach, and shows that HeyTAP can successfully guide users from their needs to specific rules.

Nowadays, users can personalize the joint behavior of their connected entities, i.e., smart devices and online service, by means of trigger-action rules. As the number of supported technologies grows, however, so does the design space, i.e., the combinations between different triggers and actions: without proper support, users often experience difficulties in discovering rules and their related functionality. In this paper, we introduce TAPrec, an End-User Development platform that supports the composition of trigger-action rules with dynamic recommendations. By exploiting a hybrid and semantic recommendation algorithm, TAPrec suggests, at composition time, either a) new rules to be used or b) actions for auto-completing a rule. Recommendations, in particular, are computed to follow the user's high-level intention, i.e., by focusing on the rules' final purpose rather than on low-level details like manufacturers and brands. We compared TAPrec with a widely used trigger-action programming platform in a study on 14 end users. Results show evidence that TAPrec is appreciated and can effectively simplify the personalization of connected entities: recommendations promoted creativity by helping users personalize new functionality that are not easily noticeable in existing platforms.

In information visualization (InfoVis), the Visualizers (graph designers and creators) have to consider multiple parameters, such as colors and graphic symbols, to obtain a chart that correctly represents a data set. Along with this, visualizers must adequately select the combination of these range of parameters to drive the observers' attention to the relevant data. When a visualizer drives the attention to relevant aspects of the information, she is providing a starting point to read the graph; this focus point might help the observer to complete the task faster and more efficiently, minimizing distraction from unimportant information. Contemporary tools for InfoVis help visualizers to a certain extent, but most of them currently do not provide insights or suggestions about the modifications needed to drive data attention. This article presents the preliminary results of an exploratory approach to draw the attention to some specific data subset selected by the graph creator, through a systematic variation of some preattentive attributes (i.e., color, texture and orientation). As a first simple method to validate the feasibility of the approach, a set of charts is created from the same source data, with exhaustive variations on preattentive attributes. All generated charts are then automatically evaluated using a salience map algorithm for data analysis images, to identify their focus attention point. After that, the algorithm chooses the chart that best emphasizes the data subset initially specified by the visualizer. To validate our approach, we have implemented a prototype tool, and preliminary results confirm that it is possible to systematically change the attention area of a chart.

End users can program trigger-action rules to personalize the joint behavior of their smart devices and online services. Trigger-action programming is, however, a complex task for non-programmers and errors made during the composition of rules may lead to unpredictable behaviors and security issues, e.g., a lamp that is continuously flashing or a door that is unexpectedly unlocked. In this paper, we introduce EUDebug, a system that enables end users to debug trigger-action rules. With EUDebug, users compose rules in a web-based application like IFTTT. EUDebug highlights possible problems that the set of all defined rules may generate and allows their step-by-step simulation. Under the hood, a hybrid Semantic Colored Petri Net (SCPN) models, checks, and simulates trigger-action rules and their interactions. An exploratory study on 15 end users shows that EUDebug helps identifying and understanding problems in trigger-action rules, which are not easily discoverable in existing platforms.

Semantic technologies and Linked Data are increasingly adopted as core application modules, in many knowledge domains and involving various stakeholders: ontology engineers, software architects, doctors, employees, etc. Such a diffusion calls for better access to models and data, which should be direct, mobile, visual and time effective. While a relevant core of research efforts investigated the problem of ontology visualization, discovering different paradigms, layouts, and interaction modalities, a few approaches target mobile devices such as tablets and smartphones. Touch interaction, indeed, has the potential of dramatically improving usability of Linked Data and of semantic-based solutions in real-world applications and mash-ups, by enabling direct and tactile interactions with involved knowledge objects. In this paper, we move a step towards touch-based, mobile interfaces for semantic models by presenting an ontology browsing platform for Android devices. We exploit state of the art touch-based interaction paradigms, e.g., pie menus, pinch-to-zoom, etc., to empower effective ontology browsing. Our research mainly focuses on interactions, yet providing support to different visualization approaches thanks to a clear decoupling between model-level operation and visual representations. Presented results include the design and implementation of a working prototype application, as well as a first validation involving habitual users of semantic technologies. Results show a low learning curve and positive reactions to the proposed paradigms, which are perceived as both innovative and useful.

Nowadays, end users can personalize their smart devices and web applications by defining or reusing IF-THEN rules through dedicated End-User Development (EUD) tools. Despite apparent simplicity, such tools present their own set of issues. The emerging and increasing complexity of the Internet of Things, for example, is barely taken into account, and the number of possible combinations between triggers and actions of different smart devices and web applications is continuously growing. Such a large design space makes end-user personalization a complex task for non-programmers, and motivates the need of assisting users in easily discovering and managing rules and functionality, e.g., through recommendation techniques. In this article, we tackle the emerging problem of recommending IF-THEN rules to end users by presenting RecRules , a hybrid and semantic recommendation system. Through a mixed content and collaborative approach, the goal of RecRules is to recommend by functionality : it suggests rules based on their final purposes, thus overcoming details like manufacturers and brands. The algorithm uses a semantic reasoning process to enrich rules with semantic information, with the aim of uncovering hidden connections between rules in terms of shared functionality. Then, it builds a collaborative semantic graph, and it exploits different types of path-based features to train a learning to rank algorithm and compute top-N recommendations. We evaluate RecRules through different experiments on real user data extracted from IFTTT, one of the most popular EUD tools. Results are promising: they show the effectiveness of our approach with respect to other state-of-the-art algorithms and open the way for a new class of recommender systems for EUD that take into account the actual functionality needed by end users.

The usage of smartphone-based virtual assistants (e.g., Siri or Google Assistant) is growing, and their spread has generally a positive impact on device accessibility, e.g., for people with disabilities. However, people with dysarthria or other speech impairments may be unable to use these virtual assistants with proficiency. This paper investigates to which extent people with ALS-induced dysarthria can be understood and get consistent answers by three widely used smartphone-based assistants, namely Siri, Google Assistant, and Cortana. We focus on the recognition of Italian dysarthric speech, to study the behavior of the virtual assistants with this specific population for which no relevant studies are available. We collected and recorded suitable speech samples from people with dysarthria in a dedicated center of the Molinette hospital, in Turin, Italy. Starting from those recordings, the differences between such assistants, in terms of speech recognition and consistency in answer, are investigated and discussed. Results highlight different performance among the virtual assistants. For speech recognition, Google Assistant is the most promising, with around 25% of word error rate per sentence. Consistency in answer, instead, sees Siri and Google Assistant provide coherent answers around 60% of times.

Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.

During the last decade, network providers are faced by a growing problem regarding the distribution of bandwidth and computing resources. Recently, the mobile edge computing paradigm was proposed as a possible solution, mainly in consideration of the provided possibility of transferring service demands at the edge of the network. This solution heavily relies on the dynamic allocation of resources, depending on the user needs and network connection, therefore it becomes essential to correctly predict user movements and activities. This paper proposes an unsupervised methodology to define meaningful user locations from noninvasive user information, captured by the user terminal with no computing or battery overhead. The data is analyzed through a conjoined clustering algorithm to build a stochastic Markov chain to predict the users’ movements and their bandwidth demands. Such a model could be used by network operators to optimize network resources allocation. To evaluate the proposed methodology, we tested it on one of the largest public community’s labeled mobile and sensor dataset, developed by the “CrowdSignals.io” initiative, and we present positive and promising results concerning the prediction capabilities of the model.

This paper presents an exploratory study aimed at identifying the pain points that novice programmers experience, from the software engineering perspective, when developing and deploying smart and distributed systems, that may be classified as Ambient Intelligence (AmI) systems. The exploratory study was conducted among undergraduate students, that worked in groups for developing AmI projects during a university course. Based on their own experiences, individually and as a group, the pain points were identified and prioritized over a common architecture and a set of software development activities. The quantification of the pain points was based on the difficulty level that the students perceived on the development activities and the time they spent completing them. Results represent a starting point for the design of tools and methodologies targeted at overcoming the complexity that novice programmers face when developing AmI systems.

In the field of Ambient Assisted Living a limited amount of research aims at supporting caregivers that work with people with disabilities in assisted living facilities (ALFs). In fact, research activities on healthcare support systems in AAL mainly focus on improving the quality of life for people in their own homes or supporting nurses and doctors in hospitals. This paper explores and applies the Internet of Things paradigm in the ALFs context. In particular, we present the design, the implementation, and the experimental evaluation of a system capable of supporting the daily activities of healthcare assistants that operate in ALFs for people with physical or cognitive disabilities. The solution combines wearable and mobile technologies to improve assistance requests and anomaly detection. With this healthcare support system, caregivers can be automatically alerted of potentially hazardous situations that happen to the inhabitants while these are out of sight. Furthermore, inhabitants can require assistance instantly and from any point of the facility. We evaluated the system in two ways. We performed a functional test with two professional caregivers, and we deployed the system in an ALF in Italy for 36 hours, collecting the opinions of the involved caregivers and inhabitants.

Due to the increasing spread of location-aware applications, developers interest in user location estimation has grown in recent years. As users spend the majority of their time in few meaningful places (i.e., groups of near locations that can be considered as a unique place, such as home, school or the workplace), this paper presents a new energy efficient method to estimate user presence in a meaningful place. Specifically, instead of using commonly used but energy hungry methods such as GPS and network positioning techniques, the proposed method applies a Machine Learning algorithm based on Decision Trees, to predict the user presence in a meaningful place by collecting and analyzing: a) user activity, b) information from received notifications (receipt time, generating service, sender-receiver relationship), and c) device status (battery level and ringtone mode). The results demonstrate that, using 20 days of training data and testing the system with data coming from 14 persons, the accuracy (percentage of correct predictions) is 89.40% (standard deviation: 8.27%) with a precision of 89.04% and a recall of 89.40%. Furthermore, the paper analyzes the importance of each considered feature, by comparing the prediction accuracy obtained with different combinations of features.

This paper presents two one-switch games designed for children with severe motor disabilities, based on the GNomon framework. These mini games demonstrate that it is possible to make dynamic video games with time-dependent game mechanics and flexible layout configurations while being accessible and playable with a single switch. The games were designed in close collaboration with a team of speech therapists, physiotherapists, and psychologists from one of the Local Health Agencies in Turin, Italy. Moreover, the games have been already evaluated with a group of children with different motor impairments through a series of trials with encouraging results.

ABSTRACT Smart environments SmE are a growing combination of various computing frameworks (ubiquitous, pervasive etc.), devices, control algorithms, and a complex web of interactions. It is at the core of user facilitation in a number of industrial, domestic, and public areas. On the basis of their application areas, SmE may be critical in terms of correctness, reliability, safety, security, etc. To achieve error‐free and requirement‐compliant implementation, these systems are designed by resorting to various modeling approaches including ontology and statecharts. This paper attempts to consider correctness, reliability, safety, and security in the design process of SmE and their related components by proposing a design time modeling and formal verification methodology. The proposed methodology covers various design features related to modeling and formal verification of SmE (focusing on users, devices, environment, control algorithms, and their interaction) against the set of the requirements through model checking. A realistic case study of a Bank Door Security Booth System (BDSB) is tested. The results show the successful verification of the properties related to the safety, security, and desired reliable behavior of BDSB. Copyright © 2013 John Wiley & Sons, Ltd.

Design and development of increasingly complex intelligent environments require rich design flows that include strong validation and verification methodologies. Formal verification techniques are often advocated, and they require formally described models of the smart home devices, their interconnections, and their controlling algorithms. Complete verification can only be achieved if all used models are verified, including individual device models. This paper proposes an approach to formally verify the correctness of device models described as UML State Charts, by checking their consistency with respect to the properties, declared in an Ontology, for the categories to which each device belongs. The paper describes the verification methodology and presents some first verification results.

Nowadays home automation, with its increased availability, reliability and with its ever reducing costs is gaining momentum and is starting to become a viable solution for enabling people with disabilities to autonomously interact with their homes and to better communicate with other people. However, especially for people with severe mobility impairments, there is still a lack of tools and interfaces for effective control and interaction with home automation systems, and general–purpose solutions are seldom applicable due to the complexity, asynchronicity, time dependent behavior, and safety concerns typical of the home environment. This paper focuses on user–environment interfaces based on the eye tracking technology, which often is the only viable interaction modality for users as such. We propose an eye-based interface tackling the specific requirements of smart environments, already outlined in a public Recommendation issued by the COGAIN European Network of Excellence. The proposed interface has been implemented as a software prototype based on the ETU universal driver, thus being potentially able to run on a variety of eye trackers, and it is compatible with a wide set of smart home technologies, handled by the Domotic OSGi Gateway. A first interface evaluation, with user testing sessions, has been carried and results show that the interface is quite effective and usable without discomfort by people with almost regular eye movement control.

This paper presents the design and architecture of an integrated environment that provides location independent and mobile access to Intelligent Domotic Environments. The envisioned architecture provides users with the ability to acquire information about devices in standard, semantic-powered, linked data formats and enables users to control house devices, independently of network and access method limitations; this enables the realization of a Web of Domotics (WoD) infrastructure. The architecture also provides the ability to perform operations, associated with the devices. A reference implementation is described, discussing the related technical foundations and issues, from general requirements to individual component design. First experimental results show that the approach is feasible and that can easily scale to wide-area deployment thanks to the adoption of open and well-established web standards.

Faceted classification is a technique originated and refined in the library science field, that recently gained a lot of attention for creating efficient search interfaces for web databases. Faceted search requires the definition of a formal representation model, a search algorithm and a responsive user interface. This paper proposes FaSet, a representation model and search algorithm supporting the implementation of faceted search engines. FaSet relies on set theory, and strikes a good balance between expressive power and ease of implementation on web architectures. The paper presents the formal definition of the model, search and ranking algorithms, and a relational mapping of data structures and algorithms that enables its efficient implementation.

Nowadays various are the situations in which people need to interact with a Personal Computer without having the possibility to use traditional pointing devices, such as a keyboard or a mouse. In the latest years, various alternatives to the classical input devices like keyboard and mouse and novel interaction paradigms have been proposed. Particularly, multimodal interactions have been proposed to overcome the limit of each input channel take alone. In this paper we propose a multimodal system based on the integration of speech- and gaze-based inputs for interaction with a real desktop environment. A real-time grammar is generated to limit the vocal vocabulary basing on the fixated area. A disambiguation method is used for inherently ambiguous vocal commands, and the performed tests show its efficiency.

This paper proposes an ontology-powered Domotic OSGi gateway (DOG) able to expose different domotic networks as a single, technology neutral, home automation system. The adoption of a standard framework such as OSGi, and of sophisticated modeling techniques stemming from the Semantic Web research community, allows DOG to go beyond simple automation and to support reasoning-based intelligence inside home environments.

The integration of semantic representation and retrieval technologies into mainstream Web applications depends on the ease of adoption and re-use of existing information and meta-data. While for textual information, analysis of the text content is quite standardized, for multimedia resources many archives and repositories resorted do define different metadata representations, creating obstacles to interoperability. The flexibility of RDF allows representing and managing all kind of meta-data and of semantic information about multimedia resources, and this paper proposes a possible strategy, based on a structure called RDF Descriptor, that allows representing, reconciling and semantically tagging multimedia resources of different media formats, and possibly coming from different sources with different representations. Experimental results show the feasibility of the approach by reporting result on cross-media and cross-archive semantic searches.

The introduction of the semantic Web paradigm in service-oriented architectures enables explicit representation and reasoning about services, via a semantically rich description of their operations. We propose an approach towards service selection and composition based upon the interpretation of user requests expressed through an informal human-computer interaction interface that employs (restricted) natural language.

Core War is a game where two or more programs, called warriors, are executed in the same memory area by a time-sharing processor. The final goal of each warrior is to crash the others by overwriting them with illegal instructions. The game was popularized by A. K. Dewdney in his Scientific American column in the mid-1980s. In order to automatically devise strong warriors, /spl mu/GP, a test program generation algorithm, was extended with the ability to assimilate existing code and to detect clones; furthermore, a new selection mechanism for promoting diversity independent from fitness calculations was added. The evolved warriors are the first machine-written programs ever able to become King of the Hill (champion) in all four main international Tiny Hills. This paper shows how playing Core War may help generate effective test programs for validation and test of microprocessors. Tackling a more mundane problem, the described techniques are currently being exploited for the automatic completion and refinement of existing test programs. Preliminary experimental results are reported.

The introduction of semantics in the next generation of the Web, the semantic Web, is strongly based on conceptual description of resources by means of semantic annotations. Effective technologies are therefore required lo correctly map the available syntactic information onto a set of relevant conceptual entities able to model the knowledge domain to which a resource belongs. In attempting to address such issue, we propose an evolutionary optimization of semantic annotation relevance which can improve text-to-concept mapping using information from both the syntactic and the semantic domains. The proposed algorithm leverages relevance information on resource contents, with respect to a subset of a given ontology, and performs several ontology navigation steps for extracting the set of most relevant annotations, in terms of semantic expressiveness. The fitness function of the algorithm is strongly time dependent since the set of annotation to be refined may vary according to user requests, to changes in the domain ontology and is related to the granularity of the annotation set.

This paper analyzes corewar, a very peculiar computer game popular in mid 80's where different programs fight in the memory of a virtual computer. The /spl mu/GP, an evolutionary assembly-program generator, is used to evolve efficient programs, and the game is exploited to evaluate new evolutionary techniques. The paper introduces a new migration model that exploits the polarization effect and a new hierarchical coarse-grained approach applicable whenever the final goal can be seen as a combination of semi-independent sub goals. Additionally, two very general enhancements are proposed. Analyzed techniques are orthogonal and broadly applicable to different real-life contexts. Experimental results show that all these techniques are able to outperform a previous approach.

Searching the Web proved to be a critical task in which both user satisfaction and speed requirements must be satisfied. Nowadays search engines provide amazing capabilities of searching resources on the Web though they are still based on text indexing and seldom exploit semantics of resource content. Therefore they sometimes fail on the identification of query context, providing results that are not relevant with respect to user needs; this is especially true for nontrained users. The semantic Web specifically addresses such an issue by providing means to define resources and query semantics using ontologies and semantic annotations. We propose a concept-based search paradigm for document retrieval. We define a new representation of the involved information space, introducing the notion of conceptual spectrum to identify the global topic landscape of Web resources and queries. We exploit such a representation to design and implement a prototypical version of a concept-based search engine. We compare the proposed approach to a traditional keyword-based engine, on a specific domain. Results are promising and show the approach feasibility.

Current automotive systems are integrating more and more electronic components in the handling and performance areas, for supporting advanced comfort and safety features. The effects of component or network failures raise serious concerns about the overall vehicle stability and safety. This work proposes a methodology for analyzing at the system level (taking into account both mechanical and electronic components) the implications of transient faults in the electronic part on the overall vehicle response. A prototypical fault injection environment is also presented, and experimental results show how safety specifications for components can be derived from performance objectives set at the vehicle level.

As an increasing number of users access information on the World Wide Web, there is a opportunity to improve well known strategies for Web prefetching, dynamic user modeling and dynamic site customization in order to obtain better subjective performance and satisfaction in Web surfing. We propose a new method to exploit user navigational path behavior to predict, in real-time, future requests. Real-time user adaptation avoids the use of statistical techniques on Web logs by adopting a predictive user model. We designed a new model derived from the finite state machine (FSM) formalism together with an evolutionary algorithm that evolves a population of FSMs for achieving a good prediction rate, and we evaluated the performance of the prediction system using the concepts of precision and applicability.

In this paper, Core War, a very peculiar game popular in mid 80's, is exploited as a benchmark to improve the /spl mu/GP, an evolutionary algorithm able to generate touring-complete, realistic assembly programs. Two techniques were analyzed: coevolution and a modified island model. Experimental results showed that the former is essential in the beginning of the evolutionary process, but may be deceptive in the end. Differently, the latter enables focusing the search on specific region of the search space and lead to dramatic improvements. The use of both techniques to help the /spl mu/GP in its real task (test program generation for microprocessor) is currently being evaluated.

The paper proposes a distributed open semantic elaboration platform based on a modular multilingual enabled architecture, which includes ontology, annotations, lexical entities and search functions. The platform is implemented as a distributed set of services including: semantic annotations for document substructures (e.g. chapters, sections, paragraphs), an external annotation repository (based on XPath and XPointer technologies) that is automatically populated starting from a known ontology and a lexical representation of concept classes, and a semantic search engine used to extract and recombine relevant document fragments. Annotated resources may be XML or XHTML static or dynamic documents, and need not be stored nor modified. Preliminary experimental results are presented to show the feasibility and the advantages of the proposed approach.

As an increasing number of users access information on the World Wide Web, there is a opportunity to improve well known strategies for Web caching, prefetching, dynamic user modeling and dynamic site customization in order to obtain better subjective performance and satisfaction in Web surfing. We propose a new method to exploit user navigational path behavior to predict, in real-time, future requests. Predicting user next requests is useful not only for document caching/prefetching, it is also suitable for quick dynamic portal adaptation to user behavior. Real-time user adaptation prevents the use of statistical techniques on Web logs, and we propose the adoption of a predictive user model based on finite state machines together with an evolutionary algorithm that evolves a population of FSMs for achieving a good prediction rate.

Design verification is a crucial step in the design of any electronic device. Particularly when microprocessor cores are considered, devising appropriate test cases may be a difficult task. This paper presents a methodology able to automatically induce a test program for maximizing a given verification metric. The methodology is based on an evolutionary paradigm and exploits a syntactical description of microprocessor assembly language and an RT-level functional model. Experimental results show the effectiveness of the approach.

Technology advances allow integrating an entire system on a single chip, including memories and peripherals. The testing of these devices is becoming a major issue for chip manufacturing industries. This paper presents a methodology, similar to genetic programming, for inducing test programs. However, it includes the ability to explicitly specify registers and resorts to directed acyclic graphs instead of trees. Moreover, it exploits a database containing the assembly-level semantics associated with each graph node. This approach is extremely efficient and versatile: candidate solutions are translated into source-code programs allowing millions of evaluations per second. The proposed approach is extremely versatile: the macro library allows the target processor and the environment to be changed easily. The approach was verified on three processors with different instruction sets, different formalisms and different conventions. A complete set of experiments on a test function is also reported for the SPARC processor.

Fault-tolerant circuits are currently required in several major application sectors, and a new generation of CAD tools is required to automate the insertion and validation of fault-tolerant mechanisms. This paper outlines the characteristics of a new fault-injection platform and its evaluation in a real industrial environment. The fault-injection platform is mainly used for assessing the correctness and effectiveness of the fault tolerance mechanisms implemented within ASIC and FPGA designs. The platform works on register transfer-level VHDL descriptions which are then synthesized, and is based on commercial tools for VHDL parsing and simulation. It also details techniques devised and implemented within the platform to speed-up fault-injection campaigns. Experimental results are provided, showing the effects of the different techniques, and demonstrating that they are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.

The problem of assisting people with special needs is assuming a central role in our society, and information and communication technologies are asked to have a key role in aiding people with both physical and cognitive disabilities. This paper describes an eye tracking system, whose strong points are the simplicity and the consequent affordability of costs, designed and implemented to allow people with severe motor disabilities to use gaze as an input device for selecting areas on a computer screen. The motivation for this kind of input device, together with the communication impairments that it may help to solve are reported in the paper, that then describes the adopted technical solution, compared to existing approaches, and reports the results obtained by its experimentation.

When designing a VLSI circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising a sample safety-critical device. Designers were permitted to assess the effects of transient faults, automatically add fault-tolerant structures, and validate the results working on the same circuit descriptions and acting in a coherent framework. The evaluation showed the effectiveness of the proposed environment.

This article addresses the problem of initializing synchronous sequential circuits, that is, of generating the shortest sequence able to drive the circuit to a known state, regardless of the initial state. Logic initialization is considered, being the only one compatible with current commercial tools. A hybrid Genetic Algorithm is proposed, which combines general ideas from evolutionary computation with specific techniques, well suited to the addressed problem. For the first time, experimental results provide data about the complete set of ISCAS'89 circuits, and show that, despite the inherent algorithm incompleteness, the method is capable of finding the optimum result for the considered circuits. A prototypical tool implementing the algorithm found better results than previous methods.

This paper deals with the diagnosis of faulty embedded RAMs and outlines the solution which is currently under evaluation within STMicroelectronics. The proposed solution exploits a BIST module implementing a March algorithm, defines a wrapper allowing its interface with a TAP controller, and describes a diagnostic procedure running in the external ATE software environment. The approach allows one to test multiple modules in the same chip through a single TAP interface and is compliant with the proposed P1500 standard for Embedded Core Test. Some preliminary experimental results gathered using a sample circuit are reported, showing the effectiveness of the proposed solution in terms of area and time requirements.

The ASIC design flow is rapidly moving towards higher description levels, and most design activities are now performed at the RT-level. However, test-related activities are lacking behind this trend, mainly since effective fault models and test pattern generation tools are still missing. This paper proposes techniques for implementing a high-level ATPG. The proposed algorithm mixes a code coverage-oriented approach with fault-oriented optimizations. Moreover, it exploits a fault model at the RT-level that enables efficient fault simulation and guarantees good correlation with gate-level fault coverage. Experimental results show that the achieved results are comparable or better than those obtained at the gate level or by similar RT-level approaches.

Testing is a crucial issue in SOC development and production process. A popular solution for SOCs that include microprocessor cores is based on making them execute a test program. Thus, implementing a very attractive BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor. The method can be partially automated and combines ideas from traditional functional approaches and from the ATPG field. We assess the feasibility and effectiveness of the method by applying it to a 8051 core.

Testing is a key issue in the design and production of digital circuits and the adoption of built-in self test techniques is increasingly popular. This paper shows an application in the field of electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. A three-phase optimization algorithm is exploited for determining the structure of a built-in self test architecture that is able to achieve good fault coverage results with a reduced area overhead. Experimental results show that the attained fault coverage is substantially higher than what can be obtained by previously proposed methods with comparable area requirements.

In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis with designers working exclusively at the RT-level, and design productivity is greatly enhanced. However, in the new design flow, validation still remains a challenge: while new technologies based on formal verification are only marginally accepted, standard techniques based on simulation are beginning to fall behind the increased circuit complexity. This paper proposes a new approach to simulation-based validation, in which a genetic algorithm helps the designer in generating useful input sequences to be included in the test bench. The technique has been applied to an industrial circuit, showing that the quality of the validation process is increased.

The current digital systems design trend is quickly moving toward a design-and-reuse paradigm. In particular, intellectual property cores are becoming widely used. Since the cores are usually provided as encrypted gate-level netlist, they raise several testability problems. The authors propose an automatic approach targeting processor cores that, by resorting to genetic algorithms, computes a test program able to attain high fault coverage figures. Preliminary results are reported to assess the effectiveness of our approach with respect to a random approach.

This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Testing is a key issue in the design and production of digital circuits and the adoption of Built-In Self-Test (BIST) techniques is increasingly popular. In this paper, the Selfish Gene algorithm is adopted for determining the logic for a BIST architecture based on Cellular Automata (CA). A Genetic Algorithm has already been proposed for identifying good BIST architectures based on CA. However, by adopting 2-bit cells, such a method introduced a significant area overhead. Thanks to the adoption of the new and more powerful search engine, we were able to identify simpler BIST structures with a lower area overhead, but still able to obtain the same fault coverage.

C/sup 2/BIST (Circular CA BlST) is a Built-In Self Test (BIST) architecture for sequential circuits based on Cellular Automata (CA). When CA cells implement suitable rules, this structure shows good test generation capabilities, reaching high fault coverage. The main characteristic of this approach is that the same CA is used for both generation and compaction, leading to a trade-off between attained fault coverage and area overhead more favorable than other BIST approaches. On the other hand, the main problem is that the circuit, during the test phase, may enter a loop early, reducing the attained fault coverage. The paper analyzes this problem and proposes a solution based on the partial reset technique, that is able to break cycles by exploiting the circuit flip-flops synchronous reset signal with a small area overhead with respect to the basic C/sup 2/BIST architecture. Experimental results allow a quantitative evaluation of the effectiveness of this approach.

In the last decade, researchers devoted much effort to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application, circuits are subjected to an activity level higher than the normal one: the extra power consumption due to test application may thus cause severe hazards to circuit reliability. Moreover, it can dramatically shorten battery life when periodic testing of battery-powered systems is considered. In this paper we propose an algorithm to design a test pattern generator based on cellular automata for testing combinational circuits that effectively reduces power consumption while attaining high fault coverage. Experimental results show that our approach reduces the power consumed during test by 34% on average, without affecting fault coverage, test length and area overhead.

This paper focuses on observability, one of the open issues in high-level test generation. Three different approximate metrics for taking observability into account during RT-level ATPG are presented. Metrics range from a really naive and optimistic one to more sophisticated analysis. Metrics are evaluated including them in the calculation of the fitness function used in a RT-level ATPG. Advantages and disadvantages are illustrated. Experimental results show how sharp observability metrics are crucial for making effective RT-level ATPG possible: test sequences generated at RT-level outperform commercial gate-level ATPGs on some ITC99 benchmark circuits.

In the design flow of digital VLSI circuits, modern state-of-the-art computer-aided design techniques implemented in automatic synthesis and optimization tools can handle designs with hundreds of flip-flops. However, many design steps are not guaranteed to be correct, either due to human intervention or to software bugs. The final correctness of the produced circuit, therefore, heavily depends of the existence of an accurate and effective verification phase. This paper presents a new verification methodology suitable for use when the equivalence between two gate-level versions of the same circuit must be verified (e.g., after an optimization step); the approach is based on genetic algorithms and, while sometimes sacrificing exactness, is able to handle large circuits and give designers the opportunity to trade off CPU time with confidence on the result. The proposed methodology is able to fruitfully integrate the results provided by an exact verification tool, dramatically increasing the confidence on the validity of an optimization process. A prototypical tool has been developed and preliminary experimental results that support this claim are shown in the paper.

Starting from a different view of natural evolution, namely that of English biologist R. Dawkins, called the selfish gene theory, a new evolutionary computation approach can be developed, the selfish gene (SG) algorithm. This paper presents a significant improvement to the SG algorithm that is able to find and exploit linkages among different genes thanks to the evolution of isolated groups called clans. The resulting SG-Clans algorithm is shown to be able to find the absolute maximum of Holland Royal Road functions, which were specifically designed to create insurmountable difficulties for a wide class of hill-climbing approaches. We support experimental evidence that SG-Clans shares the speed of a hill-climber with the ability of broadly exploring the search space.

We have presented VEGA2: a Genetic Algorithm-based approach to the problem of equivalence verification of sequential circuits. Although sacrificing the exactness of the verification, the advantages of such an approach lie in the ability to handle large designs and in the possibility to easily trade off CPU time with confidence on the result (by tuning the maximum number of generations). VEGA2 is not a replacement for exact verification tools, but a complement: when the complexity of the circuits prevents the use of a BDD-based algorithm, it is still able to provide meaningful results. We also presented a prototypical tool and experimental analysis that shows that VEGA2 is able to provide a larger number of correct results than both an exact method and the previous GA-based approach. Thus it is able increase confidence on the validity of an optimization process.

This paper presents a new integrated approach to logic optimization for sequential circuits. The approach is based on the redundancy addition and removal algorithm, which is based on automatic test pattern generation (ATPG) techniques, and improves it using symbolic techniques based on BDDs. The advantage of the integrated approach lies in the ability of Symbolic Techniques to provide exact and extensive information about the sequential behavior of the portion of the circuit that is of interest to the logic optimization algorithm. Experimental results are provided that show the superiority of the approach to the original ATPG-based optimization approach.

Tools for evaluating the worst-case peak power consumption of sequential circuits are highly useful to designers of low-power circuits. Previously proposed methods search for the initial state and the couple of vectors with maximum consumption, without fully considering the reachability of the initial state. This paper shows that this approach can lead to a significant underestimation of the maximum peak power consumption and proposes a new algorithm that overcomes this drawback. Experimental results show that for many circuits the algorithm is able to provide better results than those known up to now, while an approximate version is able to deal even with the largest benchmark circuits.

High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to genetic algorithms. Experiments show the excellent fault coverage provided by the RT-level test patterns, when applied at the final gate-level. The approach, being based on a high-level representation, promises to be particularly suited where gate-level ATPGs are often inefficient, mainly for large circuits and for control-intensive designs.

Combining different techniques for sequential automated test pattern generation (ATPG) can help overcome their respective limits and exploit their advantages. In this paper, a hybrid technique resulting from mixing topologic and symbolic approaches to the sequential ATPG problem is presented. Macros are first identified within the circuit (possibly resorting to RT-level knowledge of circuit architecture). Information about macro behavior is then computed and efficiently stored resorting to symbolic techniques. A topological tool exploits this information during the ATPG process to speed-up the propagation task and to identify early unsuccessful choices. Experimental results are reported, demonstrating that the method is able to improve the efficiency of a topological ATPG in terms of required CPU time and attained fault coverage, especially on medium-sized control-dominated circuits.

This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level. The main problem of using behavioral information for ATPG is the mismatch of timing models between the behavioral- and gate-levels. Theoretical analysis shows that the definition of the concept of dominated sequences captures the needed link between the levels. To validate the concept correctness, and to show how it can be profitably exploited, a prototypical hierarchical ATPG is presented, and experimental results show that the performance of a simple ATPG algorithm that is able to exploit behavioral information is much higher than a much more sophisticated gate-level tool.

Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.

A new approach for sequential circuit test generation is proposed that combines software based testing techniques at the high level with test enhancement techniques at the gate level. Several sequences are derived to ensure 100% coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach.

This paper proposes a method to enhance topological ATPG algorithms by exploiting some information computed through symbolic techniques. Since symbolic techniques can only be applied to small circuits, suitable circuit portions (named macros) are first selected, and then symbolic techniques are used to analyze their state graphs. The topological ATPG algorithm benefits from this analysis to bound its search tree. Experimental results show that the proposed approach is effective in reducing the required CPU time and increasing both the Fault Coverage and the Fault Efficiency. When high-level information about the circuit behavior and structure is available, it can be fruitfully exploited for macro selection.

While modern state-of-the-art optimization techniques can handle designs with up to hundreds of flip-flops, equivalence verification is still a challenging task in many industrial design flows. This paper presents a new verification methodology that, while sacrificing exactness, is able to handle larger circuits and give designers the opportunity to trade off CPU time with confidence on the result. The proposed methodology is able to fruitfully support an exact verification tool, dramatically increasing the confidence on the validity of an optimization process. A prototypical tool has been developed and preliminary experimental results that support this claim are shown in the paper.

This paper presents a BIST architecture for finite state machines that exploits cellular automata (CA) as pattern generators and signature analyzers. The main advantage of the proposed approach, called C/sup 2/BIST (circular cellular BIST) is that the same CA is used for generation and compaction, thus lowering substantially the area requirements. The configuration of the CA rules is performed through a generic algorithm that is shown to provide good results both in terms of fault coverage and number of reconfigurations. In many cases, no reconfiguration is necessary and the corresponding area occupation is competitive with current BIST approaches.

This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases the power consumption by 70% on average with respect to the original test pattern, generated ignoring the heat dissipation problem.

This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimization algorithm is proposed, which is able to explore the trade-off between them. The algorithm is based on a newly proposed power estimation function, and on an estimate of the expected rest length of a pseudo-random rest session. Given these estimates a Genetic Algorithm, exploiting some symbolic computations with BDDs, provides a state reencoding for the circuit. The algorithm is experimental shown both to provide good results from the power optimization point of view, and to be able to sacrifice, on the designer's request, some of the power and area optimization in favor of testability improvement.

Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.

The constantly increasing circuit size makes the sequential ATPG problem a challenging area even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation only when strictly required. In this paper we present a new Genetic Algorithm-based test generation method which exploits information coming from a logic simulator (e.g., the circuit activity and the reached states) to guide the search process, in particular in the fault excitation phase. Experimental results show the effectiveness of the proposed method when compared with other Genetic Algorithm-based test generators.

This paper presents a new approach to the automated generation of an initialization sequence for synchronous sequential circuits. Finding an initialization sequence is a hard task when a global reset signal is not available, and functional techniques often cannot handle large circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results we provide shore that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length.

This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is able to achieve good results: formal techniques can discover some bugs but can be applied to over-simplified models, only; on the other hand, statistical techniques relying on simulation often fail to find some critical cases for the protocol. Our proposed approach relies on coupling a genetic algorithm with a simulator of the system under verification. Genetic algorithms recently proved themselves excellent tools for giving good, yet approximate, solution to hard-to-solve problems. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the complexity of this problem prevents the application of exact techniques, while experimental results show that the verification results we obtained are better than one can achieve with traditional statistical methods. As an example, the approach is applied to the verification of the TCP protocol operating on a given network. A genetic algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol.

Proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a finite-state machine is modified to obtain a functionally equivalent circuit that exhibits a reduced power dissipation. The algorithm is based on a newly-proposed power estimation function that is able to quickly give an accurate estimate of the dissipated power without actually synthesizing the circuit. Given this estimate, a genetic algorithm provides a state re-encoding for the circuit. The estimation function is computed in a very efficient way by exploiting some symbolic computations with binary decision diagrams. The algorithm is experimentally shown to provide good results from the power optimization point of view, at a limited cost in terms of area increase, when compared with similar approaches.

This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.

This paper addresses the issue of identifying a Cellular Automaton able to generate deterministic input patterns to detect stuck-at faults inside an FSM. A suitable hardware structure is first identified. An evolutionary algorithm is then proposed, which directly identifies a Cellular Automaton able to reach a very good Fault Coverage. The novelty of the method consists in combining the generation of test patterns with the synthesis of a Cellular Automaton able to reproduce them. Experimental results are provided, which show that the proposed hardware architecture and algorithmic approach outperform more traditional solutions, based on ATPG tools and FSM synthesis, from the point of view of both applicability and area occupation, while reaching the same Fault Coverage.

Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-in Self-Test) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the test vectors applied to the unit under test. This paper addresses the issue of identifying a cellular automaton able to generate input patterns to detect stuck-at faults inside a finite state machine (FSM). A suitable hardware structure is first identified. A genetic algorithm is then proposed, which directly identifies a cellular automaton able to reach a very good fault coverage of the stuck-at faults. The novelty of the method consists in combining the generation of test patterns with the synthesis of a cellular automaton able to reproduce them. Experimental results are provided, which show that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one. Our approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures.

The goal of this paper is-to compare from an experimental point of view the performance of three ATPG tools for synchronous sequential circuits. The three tools are stare-of-the-art implementations of the topological, symbolic, and GA-based approaches, respectively. The environment set up for obtaining a fair comparison is described: the same hardware platform, circuit and fault list description, and detection mechanism are adopted. The obtained results allow the reader to more deeply understand the characteristics and relative advantages/disadvantages of these methods.

The partial scan approach is now widely adopted and several commercial tools support this technique. However, there is no general agreement on how to select the scan flip flops, in general each technique is tailored to a particular ATPG algorithm and results effective when coupled with the right ATPG tool. In this paper, we propose an approach suitable for GA-based ATPGs, which is barred on exploiting some information coming from the ATPG itself we compare the results of our method with the ones of the approach based on cutting the topological loops and use a GA-based ATPG to demonstrate its effectiveness in terms of fault coverage and CPU time.

The paper focuses an the constraints that the new silicon technologies impose on the implementation of partial and full scan approach. In particular the ordering of Flip-Flops inside each scan chain must be decided taking into account the capacitance constraints imposed by new technologies. The main goal of this paper is to prove that recent technologies impose a new design flow, exploiting layout information for scan chain reordering. Two algorithms are then described, which reduce both the average and the maximum distance between FFs in the chains, thus reducing the power dissipation of the circuit, too. Preliminary results, obtained through the implementation of the algorithms in the Italtel Design Environment and their application on a sample circuit, are reported.

This paper deals with automated test pattern generation for large synchronous sequential circuits and describes an approach based on genetic algorithms. A prototype system named GATTO is used to assess the effectiveness of the approach in terms of result quality and CPU time requirements. An account is also given of a distributed version of the same algorithm, named GATTO*. Being based on the PVM library, it runs on any network of workstations and is able to either reduce the required time, or improve the result quality with respect to the monoprocessor version. In the latter case, in terms of Fault Coverage, the results are the best ones reported in the literature for most of the largest standard benchmark circuits. The flexibility of GATTO enables users to easily tradeoff fault coverage and CPU time to suit their needs.

The paper describes the approach followed for testing a real circuit produced by Italtel. Both on-line and off-line testing are considered and the performance and area overheads are taken into account to meet the constraints imposed by the circuit customers. BIST is adopted to test some embedded memories, and boundary scan is exploited to activate the test and gather the results. Particular care is taken to minimize the additional logic, by using the same circuitry for both on-line and off-line testing.

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their sequential complexity. A state-of-the-art structural ATPG is extended by identifying some critical areas in the circuit and resorting to symbolic techniques when such areas need to be considered. Experimental results prove that the combined approach considerably enhances fault coverage while reducing CPU time when compared to a purely topological approach.

The use of parallel architectures for the solution of CPU and memory critical problems in the electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms the reduced portability of the code, and the cost of the hardware. However, portable message-passing libraries are now available, and the same code runs on high-cost supercomputers, as well as on common workstation networks. The paper presents an effective ATPG system for large sequential circuits developed using the PVM library and based on a genetic algorithm. The tool, named GATTO has been run on a DEC Alpha AXP farm and on a CM-5. Experimental results are provided.

The paper assesses the effectiveness of the circular self-test path BIST technique from an experimental point of view and proposes an algorithm to overcome the low fault coverage that often arises when real circuits are examined. Several fault simulation experiments have been performed on the ISCAS89 benchmark set, as well as on a set of industrial circuits: in contrast to the theoretical analysis proposed in [PKKa92], a very high fault coverage is attained with a limited number of clock cycles, but this happens only when the circuit does not enter a loop. This danger cannot be avoided even if clever strategies for flip-flops ordering, aimed at reducing the functional adjacency, are adopted. Instead, we suggest that loops can be avoided and fault coverage increased by carefully choosing the initial state, and we present an approach based on binary decision diagrams and symbolic techniques to solve the problem.

Process algebras are a suitable formalism both for system-level description and for ATPG with formal verification techniques. A functional fault model for system-level descriptions is presented and experimental data are reported. The contributions of this paper are the definition of a general-purpose fault model for concurrently evolving processes and the implementation of a test pattern generation procedure, as a variant of the testing equivalence proof. A complete test system is implemented, allowing one to describe systems, describe faults and generate test patterns within the same environment.>

This paper‘ deals with the generation of diagnostic test sequences for real-size synchronous sequential circuits. A modified fault simulator is used for assessing the diagnostic power of existing detection-oriented test patterns and a diagnostic procedure for generating new ones is described. The diagnostic procedure successfully exploits symbolic FSM equivalence proof algorithms. In order to resort to product machine traversal only when really needed, special checks are perfo:rrned to verify combinational identity and identity on rt:achable states. As all faults are attributed to their equivalence class, this method may be used to build a complete and exact diagnostic tree. Experimental results on ISCAS’89 circuits show the feasibility of the’ approach ’.

Particular design environments, e.g., those based on partial scan, may prevent design for testability techniques from reducing testing to a combinational problem: ATPG for sequential devices thus remains a challenge. Random and deterministic structure-oriented techniques are state-of-the-art, but there is a growing interest in methods that resort to the automaton of the circuit. The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode. SETA generates test patterns while trying to disprove the equivalence of two automata. SETA is simulation-based: within the theoretical framework of the product machine, state-of-the-art simulation techniques are used to yield satisfactory experimental results on the ISCAS89 benchmark set.>