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Gregory F. Pfister

dblp:59/4108 · DBLP profile ↗
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13ranked-venue papers
8as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 12 · 7 first-authorSoftware engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Electronic design automation · 42% High-performance computing · 14% Interconnection networks and networks-on-chip · 12%
Software engineering, system software, and programming languages
1 paper
Programming languages and type systems · 100%

Topics — the 13 heaviest of 16, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › logic simulation
gate-level simulation
0.031986
The IBM Yorktown simulation engine · Proc. IEEE 1986
The Yorktown Simulation Engine: Introduction · DAC 1982
Software support for the Yorktown Simulation Engine · DAC 1982
Electronic design automation
hardware verification and test
0.031986
The IBM Yorktown simulation engine · Proc. IEEE 1986
The Yorktown Simulation Engine: Introduction · DAC 1982
Software support for the Yorktown Simulation Engine · DAC 1982
Electronic design automation › hardware verification and test
logic simulation
0.021982
The Yorktown Simulation Engine: Introduction · DAC 1982
Software support for the Yorktown Simulation Engine · DAC 1982
Memory systems
memory access patterns
0.011987
Memory Access Patterns of Parallel Scientific Programs · SIGMETRICS 1987
Parallel and multicore computing › parallel computing
parallel scientific computing
0.011987
Memory Access Patterns of Parallel Scientific Programs · SIGMETRICS 1987
High-performance computing
scientific computing systems
0.011987
Memory Access Patterns of Parallel Scientific Programs · SIGMETRICS 1987
Interconnection networks and networks-on-chip › network contention
hot-spot contention
0.011985
"Hot Spot" Contention and Combining in Multistage Interconnection Networks · IEEE Trans. Computers 1985
High-performance computing
message aggregation
0.011985
"Hot Spot" Contention and Combining in Multistage Interconnection Networks · IEEE Trans. Computers 1985
Interconnection networks and networks-on-chip › switching network
multistage interconnection network
0.011985
"Hot Spot" Contention and Combining in Multistage Interconnection Networks · IEEE Trans. Computers 1985
Electronic design automation
hardware simulation
0.011982
The Yorktown Simulation Engine: Introduction · DAC 1982
Memory systems
shared memory
0.011987
Memory Access Patterns of Parallel Scientific Programs · SIGMETRICS 1987
Performance modeling and evaluation › simulation › parallel and distributed simulation
parallel simulation
0.011986
The IBM Yorktown simulation engine · Proc. IEEE 1986
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor
0.011985
"Hot Spot" Contention and Combining in Multistage Interconnection Networks · IEEE Trans. Computers 1985

Methods — techniques the papers use, named apart from their topics

parallel simulation · 0.0simulation · 0.0performance modeling · 0.0state networks · 0.0interaction-oriented specification · 0.0
YearPublicationVenuePosition
2001 Aspects of the InfiniBand(tm) Architecture
abstract
The InfiniBand Architecture (IBA) is a new industry-standard architecture for server I/O and inter-server communication. It was developed by the InfiniBandSM Trade Association (IBTA) to provide the levels of reliability, availability, performance, and scalability necessary for present and future server systems, levels significantly better than can be achieved with bus-oriented I/O structures. This paper provides a brief description of IBA.
Gregory F. Pfister
CLUSTER1
2000 The Future of Populist Parallelism
abstract
Summary form only given, as follows. This keynote covers past and future history of clusters. It will extrapolate the future from an observable cycle of cluster creation that has recurred several times in the past, combining that with the pieces and the glue that will be available in the future.
Gregory F. Pfister
ICCD1
1988 A single-program-multiple-data computational model for EPEX/FORTRAN
Frederica Darema, David A. George, V. Alan Norton, Gregory F. Pfister
Parallel Comput.4
1987 Memory Access Patterns of Parallel Scientific Programs
abstract
A parallel simulator, PSIMUL, has been used to collect information on the memory access patterns and synchronization overheads of several scientific applications. The parallel simulation method we use is very efficient and it allows us to simulate execution of an entire application program, amounting to hundreds of millions of instructions. We present our measurements on the memory access characteristics of these applications; particularly our observations on shared and private data, their frequency of access and locality. We have found that, even though the shared data comprise the largest portion of the data in the application program, on the average a small fraction of the memory references are to shared data. The low averages do not preclude bursts of traffic to shared memory nor does it rule out positive benefits from caching shared data. We also discuss issues of synchronization overheads and their effect on performance.
Frederica Darema, Gregory F. Pfister, Kimming So
SIGMETRICS2
1986 The Onset of Hot-Spot Contention
Gregory F. Pfister
ICPP1
1986 The IBM Yorktown simulation engine
abstract
The IBM Yorktown Simulation Engine (YSE) is a special-purpose, highly parallel programmable machine for the gate-level simulation of logic. A YSE has been constructed at the IBM T. J. Watson Research Center. A full configured YSE could simulate up to two million gates at a speed of over three billion gate simulations per second, it is estimated that a YSE could simulate an IBM 3081 processor, at the gate level, at a rate of 1000 System/370 instructions per second. This paper describes the YSE architecture and software support.
Gregory F. Pfister
Proc. IEEE1
1985 A Methodology for Predicting Multiprocessor Performance
V. Alan Norton, Gregory F. Pfister
ICPP2
1985 The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture
Gregory F. Pfister, William C. Brantley, David A. George, Steve L. Harvey, Wally J. Kleinfelder, Kevin P. McAuliffe, Evelin S. Melton, V. Alan Norton, Jodi Weiss
ICPP1
1985 "Hot Spot" Contention and Combining in Multistage Interconnection Networks
Gregory F. Pfister, V. Alan Norton
ICPP1
1985 "Hot Spot" Contention and Combining in Multistage Interconnection Networks
abstract
The combining of messages within a multistage switching network has been proposed to reduce memory contention in highly parallel shared-memory multiprocessors, especially for shared lock and synchronization data. A quantitative investigation of the performance impact of such contention and the effectiveness of combining in reducing this impact is reported. The effect of a nonuniform traffic pattern consisting of a single hot spot of higher access rate superimposed on a background of uniform traffic was investigated. The potential degradation due to even moderate hot spot traffic was found to be very significant, severely degrading all memory access, not just access to shared lock locations, due to an effect the authors call tree saturation. The technique of message combining was found to be an effective means of eliminating this problem if it arises due to lock or synchronization contention.
Gregory F. Pfister, V. Alan Norton
IEEE Trans. Computers1
1982 Software support for the Yorktown Simulation Engine
abstract
The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. This paper describes the software support for the YSE.
E. Kronstadt, Gregory F. Pfister
DAC2
1982 The Yorktown Simulation Engine: Introduction
abstract
The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. This paper introduces the YSE and describes its top-level architecture.
Gregory F. Pfister
DAC1
1976 An approach to interactive graphic programming
abstract
The development of interactive, display oriented systems for the manipulation of online information has traditionally been an extremely difficult and prohibitively expensive effort. This paper describes an approach based on the concept of interaction oriented specification and execution of applications and state networks. The general approach is described and then illustrated with a current display application development product.
Pat Velderman, Gregory F. Pfister, Pyung June Min
DAC2