An effective layout design method for VLSI processors, called the 'macrocell approach' is presented. The approach bridges the gap between full manual layout and polycell/standard cell layout with respect to the design productivity and the performance. After precise floorplanning, functional blocks are designed into macrocells using a flexible symbolic layout method, and a VLSI chip is laid out by an automatic layout program. A 16-bit digital signal processor (DSP) was designed using 2- mu m CMOS technology. Both high packing density of 1150 transistors/mm/sup 2/ and high productivity of 6.5 transistors/day for symbolic layout were attained in the design. After fabrication, the chip operated with the first silicon, realizing high-speed operation in an application program for a 32-kb/s ADPCM CODEC (adaptive differential pulse-code modulated coder-decoder).>

A custom VLSI design technique, using an integrated CAD system is described. The design system features on the hierarchical design process and layout design capability by system designers (customers). As for application, high-performance LSI's for 16-bit CPU were developed. The LSI design was accomplished in a short period (three months with three designers) due to the hierarchical standard cell approach. The LSI chip contains about 20 K transistors in an 8.84 mm X 8.88 mm die area. High-speed operation (machine cycle = 200 ns) and a high density of 291 transistors/mm2 were obtained with low power consumption (1.2 W) owing to the mixed-MOS type standard cell library and this approach.