Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multitasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low voltage data-retention failure mechanism in flops. It analyzes the impact of design and process parameters on the data retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.

In a CMOS logic circuit, the leakage power dissipated depends on the state of the design. In this paper we propose a novel technique to use the Q-gating logic that are added to reduce power during shift to also reduce leakage power during functional standby mode of the circuit. First, we propose leakage-aware test (λ-test) vector generation that can be used to profile leakage power consumed by the circuit. This is used to identify blocks that drains excessive standby leakage power. We also propose a new partial Q-gating technique that uses the λ-test to determine the subset of flops that should be gated-off to achieve maximum simultaneous reduction in shift mode dynamic power and standby mode leakage power. A fast, test relaxation and test cube merging algorithm is used for this purpose. Experiments conducted on ISCAS and ITC benchmarks show up to 43.6% reduction in leakage power. For the partial gated design, we obtained up to 15.3% leakage power reduction and up to 6.1× reduction in shift power.

Embedded SRAM dominates modern SoCs, and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, the large increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. In the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operations and meet yield targets. In this paper, we propose a new architecture that significantly reduces the array switching power for SRAM. The proposed architecture combines built-in self-test and digitally controlled delay elements to reduce the wordline pulsewidth for memories while ensuring correct read operations, hence reducing the switching power. Monte Carlo simulations using a 1-Mb SRAM macro in an industrial 45-nm technology are used to verify the power saving for the proposed architecture. For a 48-Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it an attractive solution for 45-nm-and-below technologies.

The increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. This is aggravated by the strong demand for lower cost and power consumption, higher performance and density which complicates SRAM design process. In this paper, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow enables early SRAM yield predication and performance/power optimization in the design time, which is important for SRAM in nanometer technologies. The methodology is verified using measured silicon yield data from a 1 Mb memory fabricated in an industrial 45nm technology.

The increase of statistical variations in advanced nanometer CMOS technologies poses a major challenge for digital circuit design. In this paper, we study the impact of random variations on the delay variability of a gate and derive simple and scalable statistical models to effectively evaluate delay variations in the presence of within-die variations. The derived models are verified and compared to Monte Carlo SPICE simulations using industrial 90-nm technology. This paper provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, particularly at lower supply voltages. We also show that, for a given supply voltage, there is an optimum input slew that minimizes the relative delay variation of the gate. We present conditions to achieve this minimum. The derived analytical models account for the impact of supply voltage and output loading and can be used in early design cycle. These results are particularly important for variation-tolerant design in nanometer technologies, particularly in low-power and low-voltage operation.

Process variations are becoming of increasing importance in nanometer CMOS regime. This paper reviews the challenges associated with variability and variation-tolerant design in nanometer CMOS. It highlights how design decisions, circuit techniques, and architecture decisions are modified to address the difficulties posed by the large increase in process variations.