A serial multiplier suitable for VLSI implementation is discussed. The multiplier accepts binary operands supplied in a serial fashion, least significant bits first. The multiplier uses a canonical cell which allows calculation of a 2k length product with only k identical cells. These cells utilize the carry-save addition technique to provide a delay which exhibits only a first-order dependence on the number of bits in the product. The internal logic for generating the inputs to the carry-save adders is given. This cell directly accepts the bit-serial inputs and generates a bit-serial output. Longer binary operands can be multiplied by simply cascading identical cells without change to existing cells. A given multiplier can process shorter operands in correspondingly shorter times. Applicability of this technique to VLSI implementation of the basic multiply/add operation useful in signal processing algorithms is described.

The determination of the number of distinct state assignments for a sequential machine has generally been made by the elimination of assignments that are the result of complementation or permutation of the state variables within a basic set of state assignments. For the D-type flip-flop, however, complementation may have an effect upon the cost of the control logic for a machine, leading, as some have interpreted it, to a new distinct state assignment. In this correspondence we reconsider the effect of complementation, showing that a new state assignment is produced only if the choice of Boolean form for the excitation expressions is restricted. This development unifies a previously unresolved question in determining the number of distinct state assignments for sequential machines that are implemented with D-type flip-flops.

The minimization of switching functions involving many variables is a difficult task. This paper presents a new minimization procedure that allows this process to be implemented with reduced computational effort. This procedure, designated as the directed-search algorithm, is applicable to both manual and computer-programmed minimization. The details of the algorithm are presented and illustrated by example. Comparative run-times between another minimization program and the directed-search algorithm, as implemented in Fortran, are also given.

This correspondence is a modification of the basic SHR-optimal1state assignment procedure for the D flip-flop. Under the minimum sum-of-products (MSOP) constraint, a sequential machine with n D flip-flops has 2ntimes as many distinct state assignments and twice as many distinct state assignment columns as the other flip-flop types. This correspondence shows that even though the D flip-flop machine has 2nN total distinct state assignments, the costs of these assignments can be uniquely determined by examination of only N of these assignments. Integration of this concept into the basic SHR-optimal algorithm produces a computational saving on the order of 2n-1times.

In a recently published article, Story et al. detailed an organized search process leading to the optimum state assignment for a synchronous sequential machine. Their procedure begins with the calculation of a set of lower bounds (minimum numbers) on the costs of the excitation logic required for each possible distinct partial state assignment.

By contradictory example, the method proposed by Bubenik for selecting "an irredundant set of prime implicants" is shown to lack generality.

The nonrestoring division algorithm offers the advantages of speed and logical simplicity when working with signed, two's-complement binary numbers. The algorithm does not assure sign agreement between the calculated quotient and remainder, however, which is a disadvantage in some applications. This paper describes a postcorrection that will force sign agreement between quotient and remainder. The corrective operation is very simple to implement, especially in microprogrammed arithmetic units.

Over ten years ago, Couleur described a serial binary/ decimal conversion algorithm, the BIDEC method. This was a two-step process involving a shift followed by a parallel modification of the data being converted. With the integrated-circuit J-K flip-flop, the implementation of this two-step process requires an excessive amount of control logic. This paper presents a one-step conversion algorithm that is suitable for binary-to-decimal and decimal-to-binary conversion. A general design procedure for formulating the conversion registers as a present-state/next-state counter problem is given, along with several examples of the application of the one-step algorithm. The advantages of this new algorithm include low cost, faster operation, and hardware modularity.