This paper introduces a novel approach for a system-wide performance evaluation of Zigbee networks, in the context of large-scale lighting applications. It allows a comprehensive assessment of Zigbee networks through quantitative measurement of three key performance indicators: Reliability, Robustness, and Responsiveness. It proposes a systematic framework that injects different traffic scenarios into the network to get performance scores for each node in the network for every scenario. These scores are then passed through weighted scoring algorithms to obtain a network-level score for each performance indicator. Weighting factors are computed through the Analytic Hierarchy Process (AHP) that prioritizes multiple criteria based on merit. The framework has been deployed and tested in real-life lighting systems, considering two luminaire network topologies: open-space and corridor layouts. The results show the use of the framework for overall acceptance testing as well as identifying low-performing nodes. Thus, this paper presents a distinctive methodology and a testbed to qualitatively monitor the performance of any Zigbee network deployed for lighting solutions based on user needs.

The design of embedded wireless and multimedia applications requires temporal analysis to verify if real-time constraints such as throughput and latency are met. This paper presents a design-time analytical approach to derive a conservative upper bound to the maximum end-to-end latency of a streaming application. Existing analytical approaches often assume static application models, which cannot cope with the data-dependent execution of dynamic streaming applications. Consequently, they give overly pessimistic upper bounds. In this paper, we use an expressively richer dataflow model of computation as an application model. The model supports adaptive applications that change their graph structure, execution times, and data rates, depending on their mode of operation, or scenario. We first formalize the latency analysis problem in the presence of dynamically switching scenarios. We characterize each scenario with a compact matrix in (max, +) algebra using a symbolic execution of one graph iteration. The resulting matrices are then composed to derive a bound to the end-to-end latency under a periodic source. Aperiodic sources such as sporadic streams can be analyzed by reduction to a periodic reference. We demonstrate the applicability of the technique with dataflow models from the wireless application domain. Moreover, the method is illustrated with a tradeoff analysis in resource reservation under a throughput constraint. The evaluation shows that the approach has a low runtime, which enables it to be effectively integrated in multiprocessor design flows of streaming applications.

Embedded streaming applications require design-time temporal analysis to verify real-time constraints such as throughput and latency. In this paper, we introduce a new analytical technique to compute temporal bounds of streaming applications mapped onto a shared multiprocessor platform. We use an expressively rich application model that supports adaptive applications where graph structure, execution times and data rates may change dynamically. The analysis technique combines symbolic simulation in (max, +) algebra with worst-case resource availability curves. It further enables a tighter performance guarantee by improving the WCRTs of service requests that arrive in the same busy time. Evaluation on real-life application graphs shows that the technique is tens of times faster than the state-of-the-art and enables tighter throughput guarantees, up to a factor of 4, compared to the typical worst-case analysis.

Heterogeneous Multiprocessor systems-on-chip (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet realtime requirements. Designing HMPSoCs with predictable timing behavior is a key challenge, as the current design methods for these platforms are semi-automated, non-predictable, or support limited heterogeneity. In this demonstration, we present a design framework to rapidly generate and implement predictable HMPSoC designs. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints of the application. We also present results of a case study that computes the performance-power tradeoffs of an industrial vision application. A tool-chain targeting the Xilinx Zynq FPGA is also presented.

Heterogeneous Multiprocessor System-on-Chips (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet real-time requirements. Designing these predictable HMPSoCs is a key challenge, as the current design methods for these platforms are either semi-automated, non-predictable, or have limited heterogeneity. In this paper, we propose a design framework to generate and program HMPSoC designs in a rapid and predictable manner. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints. The experimental results show that our framework can provide a conservative bound on the worst-case throughput of the FPGA implementation. We also present results of a case study that computes the area-power trade-offs of an industrial vision application. The entire design space exploration of all configurations was completed in 8 hours. A tool-chain targeting the Xilinx Zynq FPGA is also presented.

A present-day System-on-Chip (SoC) runs a wide range of applications with diverse real-time requirements. Resources, such as processors, interconnects and memories, are shared between these applications to reduce cost. Resource sharing causes temporal interference, which must be bounded by a suitable resource arbiter. System-level analysis techniques use the service guarantee of the arbiter to ensure that real-time requirements of these applications are satisfied. A service guarantee that underestimates the minimum service provided by an arbiter results in more allocation of resources than needed to satisfy latency and throughput requirements. For instance, a linear service guarantee cannot accurately capture burst service provision by many priority-based schedulers, such as Credit-Controlled Static Priority (CCSP) and Priority-Budget Scheduling (PBS). As a result, the timing analysis of these arbiters becomes too pessimistic. This leads to unnecessary cost penalties since some SoC resources, such as SDRAM bandwidth, are scarce and expensive. This paper addresses this problem for the CCSP arbiter. The two main contributions are: (1) a piecewise linear service guarantee that accurately captures bursty service provisioning, and (2) an equivalent dataflow model of the new service guarantee, which is an essential component to integrate the arbiter with dataflow-based system-level design techniques that analyze the worst-case latency and throughput of real-time applications. The new service guarantee enables efficient resource utilization under CCSP arbitration. Experimental results of an H.263 video decoder application show that memory bandwidth savings from 26% up to 67% can be achieved by using the new service guarantee as compared to the existing linear service guarantee.