Scan based diagnostic schemes implicitly assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain can occupy a considerable area of the chip and hence should not be neglected during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains based upon fault dictionaries.

Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains.

Built-in-self-test (BIST) schemes provide on-chip circuitry to generate test vectors and to analyze output responses so that testing can be performed without using expensive external testers. The authors present a unified approach to test pattern generation and output compaction. ISCAS benchmark circuits are used to show the applicability of the proposed method.>

A new error model that considers both space and time correlation is proposed. An exact closed form expression for aliasing probability is obtained for an arbitrary test length for a large class of signature registers. The authors identify the minimum register structure that falls into this class.>

A unified scheme for test-pattern generation and output compaction using circuit-specific information is presented. It is shown that partial control over test-pattern sequence can give zero aliasing in single-output circuits and reduced aliasing in multiple-output circuits. The exact aliasing probability is obtained for multiple-output circuits under the independent bit error model for any test length. The aliasing probability for multiple-output circuits of this scheme is independent of the feedback polynomial of the multiple-input shift register (MISR). This method reduces aliasing considerably without increasing the length of the MISR by having a simple quotient detector. The approach is applied to benchmark circuits to show the applicability of the scheme to a given combinational circuit.>

In distributed systems files are replicated to enhance availability and reliability. The authors provide an algorithm based on coding theory to significantly reduce the number of signatures needed to precisely diagnose differing pages in remotely located file copies. The method needs only one message transmission. A unique feature of this method is the ability to precisely diagnose up to t differing pages with just 2t signatures, independent of the files size. The maximum number of pages in a file is determined only by the number of bits in a signature. If a signature has m bits, the proposed technique can precisely identify t(t>

A data compression technique for ROM based built-in test generators of combinational circuits is described. Some of the test pattern bits are computed using the reduced data stored in the ROM combined with the address bits accessing the ROM. Some experimental results are presented for ISCAS benchmark circuits and random data.>

The aliasing probability in single and multiple input linear automata signature registers (LASRs: linear feedback shift registers (LFSRs) and linear cellular automata) has been widely studied under the independent bit error model. Aliasing in a class of multiple-input LASRs (MILASRs) under the q-ary symmetric error model is examined. By modeling the signature analyzer as a two state Markov process, it is shown that the closed form expression previously derived for aliasing probability for multiple-input LFSRs with primitive polynomials holds for a far more general class of linear automata signature analyzers, including all multiple-input LFSRs. An easily verifiable criterion is given to determine whether a MILASR falls into this category. It is shown that for q-ary symmetric errors, the circuit complexity and the propagation delay can be minimized by using a set of m single bit LFSRs.>