In the realm of desktop and server class processors, the prevailing trend is to use out-of-order superscalar cores that exploit the hidden instruction-level parallelism in a program. In superscalar designs, the performance (as measured by the IPC, instructions committed per clock cycle) does not go up linearly with the dispatch width, say, n, due to dependencies in the program and higher branching penalties that are encountered with an increase in n. Furthermore, the area requirement of a superscalar processor grows more than linearly with n, leading to poor energy efficiency (IPC per Joule of expended energy) for higher values of n. This paper introduces FlexCore, a reconfigurable multicore datapath where the processing resources, dispatch width and operating modes (in-order, out-of-order, simultaneously multithreaded execution) are dynamically adapted based on the instantaneous needs of the executing application to avoid overcommitting any processing resource. In FlexCore, unutilized or underutilized processing components are shut down to save power and realize higher energy efficiency compared to a baseline out-of-order multicore chip with a fixed core configuration. FlexCore, regardless of the specific reconfiguration mode, always presents the same number of virtual processors to the Operating System and thus requires no OS modifications. A cycle-accurate simulation of FlexCore or many-threaded and multi-threaded applications show that significant improvements in energy efficiency are realized over the baseline design with little or no impact on performance.

The construction of trustworthy systems demands that the execution of every piece of code is validated as genuine, that is, the executed codes do exactly what they are supposed to do. Pre-execution validations of code integrity fail to detect run time compromises like code injection, return and jump-oriented programming, and illegal dynamic linking of program modules. We propose and evaluate a generalized mechanism called REV (for Run-time Execution Validator) that can be easily integrated into a contemporary out-of-order processor to validate, as the program executes, the control flow path and instructions executed along the control flow path. To prevent memory from being tainted by compromised code, REV also prevents updates to the memory from a basic block until its execution has been authenticated. Although control flow signature based authentication of an execution has been suggested before for software testing and for restricted cases of embedded systems, their extensions to out-of-order cores is a non-incremental effort from a micro architectural standpoint. Unlike REV, the existing solutions do not scale with binary sizes, require binaries to be altered or require new ISA support and also fail to contain errors and, in general, impose a heavy performance penalty. We show, using a detailed cycle-accurate micro architectural simulator for an out-of-order pipeline implementing the X86 ISA that the performance overhead of REV is limited to 1.87% on the average across the SPEC 2006 benchmarks.

We introduce an alternative instruction commitment mechanism for a Reorder Buffer (ROB)-based out-of-order processor that commits a group of consecutive instructions atomically to support a larger instruction window. The proposed mechanism makes conservative use of the ROB, by only setting up entries for the instructions that perform the latest update to a register from that group. Further, the destination registers of instructions from a group that do not hold the most recent updates to architectural registers, can be released before the group containing these instructions is committed. The net result is an augmented ROB-based datapath, which increases the effective size of the ROB as well as the effective number of physical registers. The proposed design achieves an average performance gain of about 10% and 16% on the SPEC integer and floating point benchmarks, respectively, when compared to a traditional ROB-based design. The proposed design also achieves a performance gain of slightly over 5% when compared with an aggressive design that uses checkpoints and relatively complex hardware resources.

We address the problem of improving the energy efficiency of servers that provide web-based services, including services provided through clouds. We propose an automated technique for allocating workload to servers to operate the fewest number of servers that are needed to cope with the instantaneous workload, leaving some headroom for workload surges. The technique requires no a priori knowledge about individual workloads and manages the server states explicitly. We use synthetic scripts, a small server setup and actual energy consumption measurements to show that the proposed system achieves non-trivial energy savings at typical operating regions of traditional server configurations.

We present MARSS, an open source, fast, full system simulation tool built on QEMU to support cycle-accurate simulation of superscalar homogeneous and heterogeneous multicore x86 processors. MARSS includes detailed models of coherent caches, interconnections, chipsets, memory and IO devices. MARSS simulates the execution of all software components in the system, including unmodified binaries of applications, OS and libraries.