Two different radio architecture are proposed that allow for simultaneous reception on one frequency and scanning on another frequency using only one receiver chain. This can for instance be used to scan for an alternative frequency when a handover is required in a cellular system. The architectures are based on that the signal is down-converted to a complex intermediate frequency (IF) before being down-converted to baseband. The second mixer is made adjustable so that any desired image rejection ratio (IRR) can be obtained. By adjusting the IRR and estimate how the signal quality of the desired signal is affected, the signal power at the image frequency can be accurately estimated. Based on simulations of an OFDM system with LTE-like parameters, it is found that if a degradation of 0.5-1 dB is acceptable for the desired signal, a scanning time of 1-2 ms suffice for accurate power estimation.

Communications between processing elements (PEs)in very large scale parallel systems become more challenging as the function and speed of the PEs improve continuously. Clocked I/O ports may malfunction if data read failure occurs due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughput, less power consumption in clock distribution, no constraints on clock skew and system scale, easy in design, less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, a robust vector transfer between PEs with arbitrary clock phases is achieved and the headache problem of the global synchronization is avoided.

In very high-speed CMOS cell design, the result of schematic simulation is inaccurate because of missing parasitic components, such as diodes and parasitic capacitances. Designer cannot pass enough information to the simulator by conventional transistor symbols, therefore, simulation error occurs. In this paper, we address a layout-based schematic (LBS) method for high-speed CMOS cell design. In this method, we introduce several types of MOS transistors and estimate parasitic wire capacitances by using layout knowledge. The simulation results show that the difference between LBS and real layout is much smaller, less than 3% in rise time, compared to in the worst case of up to 65% in the original schematic. This method can be applied to both digital and analog circuits and it is helpful for layout automation. Time and cost will be reduced in high-speed circuit design.

Communications between processing elements (PEs) in high speed parallel systems become a bottleneck as the function and speed of the PEs improve continuously. Clocked I/O ports in PEs may malfunction if data read failure occurs due to clock skew. To reduce the clock skew, global clock distribution is utilized, however it seems to be more difficult to use this for high speed parallel systems in the future. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. This method has these features: high data throughput; low power consumption; no constraints on clock skew and system scale; flexibility in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. Using a jitter injected test signal, robust vector transfer between PEs with arbitrary clock phases is achieved without global synchronization.