Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Thomas Stiefmeier

dblp:60/1371 · DBLP profile ↗
← Back
7ranked-venue papers
0as first author
0since 2021 · last 2012
0000-0001-8758-6822ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Artificial intelligence and machine learning · 1Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 67% Hardware accelerators and domain-specific architectures · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
dynamic reconfiguration
0.012004
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs · FPGA 2004
Hardware accelerators and domain-specific architectures
network accelerator
0.012004
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs · FPGA 2004
Reconfigurable computing and FPGAs › reconfigurable architecture
reconfigurable functional unit
0.012004
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs · FPGA 2004
YearPublicationVenuePosition
2012 Improving Game Accessibility with Vibrotactile-Enhanced Hearing Instruments
Bernd Tessendorf, Peter Derleth, Manuela Feilner, Daniel Roggen, Thomas Stiefmeier, Gerhard Tröster
ICCHP (1)5
2012 Continuous activity recognition in a maintenance scenario: combining motion sensors and ultrasonic hands tracking
Georg Ogris, Paul Lukowicz, Thomas Stiefmeier, Gerhard Tröster
Pattern Anal. Appl.3
2011 Design of a bilateral vibrotactile feedback system for lateralization
abstract
We present a bilateral vibrotactile feedback system for accurate lateralization of target angles in the complete 360 degree-range. We envision integrating this system into context-aware hearing instruments (HIs) or cochlear implants (CIs) to support users that experience lateralization difficulties. As a foundation for this it is vital to investigate which kind of feedback and vibration patterns are optimal to provide support for lateralization. Our system enables to evaluate and compare different encoding schemes with respect to resolution, reaction time, intuitiveness and user dependency. The system supports bilateral vibrotactile feedback to reflect integration into HIs or CIs worn at both ears and implemented two approaches: Quantized Absolute Heading (QAH) and Continuous Guidance Feedback (CGF). We provide a detailed description of our hardware that was designed to be also applicable for generic vibrotactile feedback applications.
Bernd Tessendorf, Daniel Roggen, Michael Spuhler, Thomas Stiefmeier, Gerhard Tröster, Tobias Grämer, Manuela Feilner, Peter Derleth
ASSETS4
2008 Activity Recognition from On-Body Sensors: Accuracy-Power Trade-Off by Dynamic Sensor Selection
Piero Zappi, Clemens Lombriser, Thomas Stiefmeier, Elisabetta Farella, Daniel Roggen, Luca Benini, Gerhard Tröster
EWSN3
2005 On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction
Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
VLSI-SoC2
2004 On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs
abstract
This work presents the hardware design of a dynamically reconfigurable function unit (RFU) to accelerate computation-intensive tasks in Medium Access Control (MAC) layers of WLANs. The function unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for the Advanced Encryption Standard (AES) as specified in upcoming WLAN standards such as IEEE 802.11i. Dynamic reconfiguration allows the processor to use arithmetic components and memory elements of the RFU not only for AES, but also for additional tasks common in the MAC-layer. With our approach it is possible to accelerate Reed-Solomon-Code generation, Cyclic Redundancy Checks as well as other encryption standards like SQUARE, Magenta and Twofish by supporting Galois Field multiplication and table look-ups. The integration of the reconfigurable unit in the processor core results in an architecture that can simultaneously support control-flow and data-flow oriented tasks. This architecture was prototyped onto a Virtex2 FPGA.
Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
FPGA3
2004 A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals
Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
FPL2