Dielectrophoresis (DEP) is a powerful technique for manipulating biological cells. Yet, its widespread application has been limited by traditional glass-based chips with static electrode configurations that often require integrated microfluidic systems. This paper presents a novel DEP array chip fabricated in a standard CMOS process, featuring a 128 × 128 electrode matrix capable of generating dynamic, programmable electric field patterns that can be tailored to meet specific requirements for different use cases. Experiments have demonstrated the ability of the chip to manipulate fibroblast and THP-1 cells, with fibroblast movement observed at a velocity of 10µm/s with a DEP frequency of 800kHz and a peak-to-peak DEP voltage of 1.8V. The chip is designed for compatibility with standard petri dishes, obviating the requirement for microfluidics and facilitating its integration with traditional cell culture protocols. Our results indicate the chip’s potential as a versatile tool for cell biology research and applications.

Capacitive sensor array (CSA) has emerged as a prominent approach in the field of biomedical detection, particularly for the analysis of cell morphology and the construction of a Cell-on-CMOS platform. To enhance overall sensitivity, this paper presents a novel 2-D vernier digital-to-time converter (2D V-DTC) with a resolution of 31.25 ps and a dynamic range of 2.56 µs. The 2-D vernier structure attains sufficient resolution while reducing the number of delay elements required, and seamlessly integrates with a counter-based controller, extending the dynamic range to effectively cover a significantly larger sensing window. The CSA biochip, fabricated in 180-nm CMOS technology, achieves results with an overall sensitivity of 880 code/fF. This achievement translates into an sensing resolution of 1.13 aF, demonstrating its potential to further advance the development of CMOS-based cell-monitoring platform.

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of [email protected] and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTHmeasurement scheme is about 2-7mV at TT corner across temperature range from 85°C to -45°C, and post-layout simulations show the resolution of the digital read-out scheme isTHdistributions agree well with Monte Carlo simulation results.

This paper presents a 1.0Mb high-performance 0.6V VMIN6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is [email protected] and [email protected].

We present a 55nm 128Kb 6T SRAM with a variation-tolerant dual-tracking Word-Line Under-Drive (WLUD) to improve the RSNM and a Data-Aware Write-Assist (DAWA) scheme. Error free full functionality without redundancy is achieved from 1.5V down to 0.55V with area overhead of 4% for WLUD and 14% for DAWA, respectively. The measured power overheads (FF, 25oC) are 1.1% for WLUD and 3.3% for DAWA at 1.0V (3% and 5.3% at 0.6V), respectively. The maximum operating frequency is 940MHz (360MHz) at 1.0V (0.6V) and 25oC. The measured power/performance (FF, 25oC) is 0.117mW/MHz (0.023mW/MHz) at 1.0V (0.6V).

In this paper, we study circuits implemented using high-density arrays composed of vertical slit field effect transistors. This layout style could dramatically increase transistor density and, therefore, reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks, pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.

In this paper, we study circuits implemented using high-density arrays composed of Vertical Slit Field Effect Transistors. This layout style could dramatically increase transistor density and therefore reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit-level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing.

In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate, transistor-array-based layout. Interconnects on all metal layers are strictly parallel and can be manufactured by an optical proximity correction free process. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced.

In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate transistor-array-based layout. Interconnects on all metal layers are uni-directional and can be manufactured by an OPC-free process [4]. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced.

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.

Advancements in IC manufacturing technologies allow for building very large devices with billions of transistors and with complex interactions between them encapsulated in a huge number of design rules. To ease designers' efforts in dealing with electrical and manufacturing problems, regular layout style seems to be a viable option. In this paper we analyze regular layouts in an IC manufacturability context and define their desired properties. We introduce the OPC-free IC design methodology and study properties of cells designed for this layout style that have various degrees of regularity.

Real time video streaming over wireless networks is not trivial because of the two characteristics of the wireless networks - (1) smaller bandwidth and (2) unreliable transmission media. An adaptive real-time video streaming scheme that uses the layered video technique is proposed. Two attributes that are used to determine the network situation and then adjust the sending rate accordingly are loss rate and round trip time (RTT). Since the unreliable media cause of packet loss in the wireless environment is rate-independent, a method that can separate the rate-independent loss from the congestion loss is needed. We use inter-arrival time between two received packets to identify if an out of order packet was received in time to do the packet loss separating. When a congestion situation is determined, the sending rate of the sender is dropped down one layer; when an unloaded situation is determined, the sending rate of the sender is raised up one layer. In this way, the adaptive real-time video streaming can be achieved for wireless networks.