Evaluating the reliability of deep neural network (DNN) applications is essential to assess efficient error resilience techniques and deploy artificial intelligence (AI) on safety-critical embedded systems. This work presents a novel methodology for assessing the reliability of DNN models deployed on microcontrollers using software-level fault injection. A new tool was developed, on top of the TensorFlow Lite library for C/C++, to inject faults into memory and CPU registers during DNN inference. Providing a portable, fast, and configurable approach for injecting multiple fault types. The proposed framework was validated with two case studies, using a variety of literature-endorsed models and datasets, the results provide a comparative analysis of DNN reliability versus register and memory bit flips, induced by transient faults.

Convolutional Neural Networks (CNNs) are vulnerable to undetectable manipulated inputs that reduce model accuracy. There are several methods to counter these Adversarial Attacks, however, resource-constrained systems require simpler solutions due to memory and processing limitations. This work explores the application of single-layer redundancy to implement a dynamic model in TensorFlow CNNs and its impact on mitigating Adversarial Attacks.

Laser fault injections induce transient faults into ICs by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical, or logical. At the electrical level, the classical laser fault injection model is based on the addition of current sources to the various sensitive nodes of CMOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of ICs designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR-drop that contribute to the fault injection process. This paper describes our research on the assessment of this contribution. It shows through simulation and experiments that during laser fault injection campaigns, laser-induced IR-drop is always present when considering circuits designed with deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that allows the use of the model to simulate laser-induced faults at the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor of up to 2.4 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems.

The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumption without compromising the circuit performance or its robustness. Asynchronous circuits have demonstrated to be an excellent solution to help designing robust and energy-efficient circuits required for the Internet-of-Things and the mobile applications. Their local synchronization mechanisms, based on handshake protocols, make them perfectly suitable for exploiting dynamic power management techniques, such as Adaptive Body Biasing (ABB) in FD-SOI technologies. Indeed, the circuit activity is simply detected by using the already existing handshake signals, enabling the application of different ABB strategies with almost no modification to the original asynchronous circuit. As the synchronization mechanisms are local to small logic blocks, the ABB strategy is able to target from small to large body bias domains. In order to manage such a technique, an analog dedicated standard cell has been designed to body bias small regions. Depending on the body bias domain granularity, an appropriated number of these specific cells is inserted exactly as logic standard cells during the back-end operations. Additionally, the robustness of asynchronous circuits makes possible changing the transistor threshold voltage on-the-fly, a requirement for applying ABB schemes without complex power management issues.

Asynchronous circuits, as any IC, are vulnerable to hardware Trojans (HTs), which might be maliciously implanted in IC designs during outsourced fabrication phases. In this paper, a new testing technique to detect HTs by exploiting the regular side-channel properties of quasi-delay insensitive (QDI) asynchronous circuits is proposed. The technique does not need neither additional circuitry nor significant adjustments in the post-fabrication testing phase. Simulation results show that the proposed technique is able to detect HTs with dimensions smaller than 1% of the original circuit.

Dynamically scaling down the voltage of integrated systems is an effective technique for enabling low-power operation modes. The system is partitioned into several subcircuits, and inactive parts are dynamically biased with low voltages. Additionally, controlling the body bias of subcircuits allows modifying transistor threshold voltages for optimizing speed and power. Both these techniques shift voltages to different levels, demanding dedicated level shifter cells. This paper presents a novel level shifter CMOS architecture able to operate with ultra-low voltages at the expense of reasonable delay and power penalty. Results in technology UTBB FD-SOI 28 nm show the proposed architecture would be controllable by subcircuits of systems operating at 0.19 V, which is lower than the minimum voltage (0.32 V) reachable by the most effective state-of-the-art level shifter cell simulated under the same conditions.

Designing secure integrated systems requires methods and tools dedicated to simulating that early design stages' the effects of laser-induced transient faults maliciously injected by attackers. Existing methods for simulation of laser-induced transient faults do not take into account IR drop effects that are able to cause timing failures, abnormal reset, and SRAM flipping. This paper proposes a novel standard CAD tool-based method allowing to simulate laser-induced faults in large-scale circuits. Thanks to a power-grid network modeled by a commercial IR drop CAD tool, an additional transient current component causing laser-induced IR drop is taken into consideration. This current component flows from Vdd to Gnd and may have a significant effect on the fault injection process. The method provides fault sensitivity maps that enable a quick assessment of laser-induced fault effects on the circuit under analysis. As shown in the results, the number of induced faults is underestimated by a factor as large as 3.1 if laser-induced IR drop is ignored. This may lead to incorrect estimations of the fault injection threshold, which is especially relevant for the design of countermeasure techniques for secure integrated systems. Simulation times regarding four different circuits are also presented in the results section.

Laser fault injection attacks induce transient faults into ICs by locally generating transient currents capable of temporarily flipping the outputs of logic gates. Laser fault injection may be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the general laser-fault injection model is based on the addition of current sources to the various sensitive nodes of CMOS transistors. This type of electrical model does not take into account the large transient current components also induced between VDD and GND as a result of laser illumination. Such current components have no direct effect on the logic gate output nodes. Still, they provoke a significant IR-drop that may, in turn, contribute to the fault injection process. This paper describes our research on the assessment of this contribution. It introduces an upgraded electrical model taking the laser-induced IR-drop into account. It also proposes a methodology that allows the model's use to simulate laser-induced faults at electrical level in large-scale circuits. On the basis of simulations with a case-study circuit, we found that, depending on the parameters of the laser pulse, the number of injected faults may be underestimated by a factor as large as 48 if the laser-induced IR-drop is ignored. This may lead to incorrect estimations of the fault injection threshold, which is especially relevant for the design of countermeasure techniques for secure integrated systems.

The C-element is a fundamental component in asynchronous circuits and quite used in synchronous circuits to mitigate transient faults. This work evaluates the transient-fault effects on the traditional dynamic, conventional, weak feedback, and symmetric C-element's implementations. An evaluation methodology is developed by means of fault-injection simulations at transistor level. Unlike existing methods, the methodology in this work is able to deal with the C-element function's particularities. In addition, C-element cells in different transient-fault robust versions are designed by using techniques based on sizing and transistor insertion. Results in terms of delay, power consumption, area, and fault-transient robustness show the best C-element options for the design of more robust systems.

A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.

This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in order to save design time. Furthermore, fault-tolerant IC design issues and results in area and performance were compared with a non-protected microprocessor version