A new framework is proposed to generate compact quality tests to detect small delay defects by activating and propagating transition faults only along implicitly kept sensitizable critical paths. It is shown how to implicitly generate functions to derive tests for the proposed framework. The novelty of the method relies on a multivalued algebra that is used to generate the test functions with a single circuit traversal, independent of the number of critical paths. Experimental results demonstrate the effectiveness of the method.

This paper examines the problem of exact delay fault grading in non-scan sequential circuits using a sequence of test patterns that are applied with a rated clock. Delay faults ending at flip-flops are latched as uncorrelated errors. The errors latched on flip-flops by previous tests may enhance the at-speed delay fault coverage for each pattern in the sequence. In addition, the propagation of errors (and the faults they represent) may be facilitated by other latched errors as well as potential delayed transitions activated by each at-speed test application. An exact grading method is presented and its impact over existing methods is demonstrated experimentally

A novel function-based method for error propagation is proposed for exact delay fault coverage, using a single rated clock for fault activation under any delay fault model. Sequential circuits without full scan are considered. A latched error at a flip-flop represents one or more delay faults and is allowed to propagate to an observable point with or without the support of other latched errors. Existing methods allow only one flip-flop to have an error during the propagation phase to simplify the process of error propagation at the expense of decreased fault coverage. The advantage of the proposed method is demonstrated experimentally using the path-delay-fault model with more than 20% improvement in fault coverage.

The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with the support of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds on the memory requirements.

A recent work describes an ATPG for path delay faults that limits the power dissipated by the test patterns to a given bound. However, the power dissipated by the intermediate patterns while applying the test patterns in a sequence is not considered. Experiments with test patterns derived from different ATPGs has shown that the switching activity due to intermediate patterns dissipate considerable power. This paper proposes a method to incorporate stability functions in a functional ATPG to derive test vectors that guarantee reduced power dissipation by the intermediate patterns without loss in PDF coverage.

Compact high quality test sets to detect small delay defects can be generated using the transition fault model by insisting that events are activated and propagated only along the critical paths for each transition fault, implicitly kept in a zero-suppressed binary decision diagram. This paper shows how to implicitly generate test functions for the described high quality transition fault model. The novelty of the method relies on a multivalued algebra that is used to generate the test functions with a single circuit traversal.

In this paper we propose an implicit test pattern generation method so that many path delay faults are covered and the dissipated power satisfies a given bound. Typical delay values are considered from an accurate gate delay model. We use a timed ATPG that combines function-based and structural (PODEM-like) methods for faster test generation, which is also more accurate in sequential circuits.