This work presents the Procket DFT architecture which is developed to improve manufacturability (time-to-market, high quality and ease of chip/board/system bring-up) thus reducing the time for chip ramp and initial system bring-up. Common DFT structures are used on all chips in the family and a similar process is used to access all on-chip DFT structures from the system. This architecture allows for reconfigurable scan chains, which includes parallel chains for tester access, and various sections of the chains during board/system bring up to allow for easy diagnosis. Access to all debug features is via the IEEE 1149.1 ports which allows the same software to be used for chip, board and system debug.

This paper describes the use of a high-level view (functionalview) of a clock regenerator circuit for generating effective andinexpensive manufacturing tests. It is shown that the tests generatedfrom the traditional, structural view add hardwareoverhead, increase design time and potentially lower effectiveyield when compared to the tests generated from the functionalview. A test generation procedure is described and successfullyused on a microprocessor design.

Digital designs, implemented in CMOS technology, have increasingly used tri-state logic (pass gates) to increase clock speed. It is also known that tri-state logic based designs have poor testability, as measured by the single stuck-at fault model, due to the proliferation of "possible-detect" faults. Design for test techniques that have been developed to address testability issues with tri-state logic designs, often incur hardware and cycle-time overheads. In this paper, we discuss the effect of one class of "possible-detect" faults and the implicit ability of a test pattern set in detecting such faults on real hardware.

Performance degradation due to insertion of BIST logic into high-speed designs has been analyzed. A framework to introduce BIST into random logic circuits, without causing timing violations has been proposed. Various heuristics for selecting flip-flops for BIST have been developed and studied in detail. Experimental results indicate an improvement in performance while optimizing fault coverage and area overhead.

Article Free Access Share on Extraction of a high-level structural representation from circuit descriptions with applications to DFT/BIST Authors: Ishwar Parulkar Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CAView Profile , Melvin A. Breuer Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CAView Profile , Charles A. Njinda Vertex Semiconductors, 1060, Rincon Circle, San Jose, CA Vertex Semiconductors, 1060, Rincon Circle, San Jose, CAView Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994 Pages 345–356https://doi.org/10.1145/196244.196417Online:06 June 1994Publication History 4citation145DownloadsMetricsTotal Citations4Total Downloads145Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and to develop an efficient and useful SLTG system for combinational circuits. The basic idea is to make use of as many GLTG concepts as possible without modeling a CMOS circuit at the gate level. Based on the analysis of CMOS circuits and faults, a SLTG system called SWiTEST has been developed. This system can deal with bridging, transistor stuck-open, transistor stuck-on and stuck-at faults. It employs both logic and current (IDDQ testing) monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework of this system is PODEM-based. To be applicable to switch level circuits, the basic PODEM algorithm has been enhanced to deal with concepts such as multiple objective selection, search-based backtracing and incremental event-driven logic implication. Experimental results indicate that SWiTEST is quite efficient in both CPU time and memory usage.>

A systematic approach has been developed to provide designers with a set of testable versions for a given design, ranging from the minimal test time solution to the minimal area overhead solution. The designer thus has the flexibility to make the necessary tradeoff between area overhead and test time depending on the constraints of the design under consideration. By employing an expert selection developed previously, the system can be extended to operate as an intelligent BIST (built-in self-test) design advisor. Experiments have been performed on several circuits generated by MABAL, a high-level synthesis tool, to demonstrate the performance of this approach.>

The authors present a procedure for merging on-chip controllers for BIST (built-in self-test) circuitry to reduce hardware overhead. Instead of starting with one minimal state assignment and then performing state, input, and output encoding, one picks the 1-hot code state assignment and implicitly searches the space of minimum prime compatible state covers to obtain an optimal merged controller. This procedure uses knowledge of the greatest lower bounds on states, arcs, next-state, and the output logic of the merged controller to prune the search space.>

Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.>