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Ayakannu Mathialagan

dblp:60/5775 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1981
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 54% Integrated circuit design · 23% Electronic design automation · 23%
Theoretical computer science
1 paper
Mathematical optimization · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › microprogramming
control memory minimization
0.011981
Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers · IEEE Trans. Computers 1981
Processor architecture and microarchitecture › microprogramming
microprogrammed control
0.011981
Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers · IEEE Trans. Computers 1981
Integrated circuit design
circuit design
0.011980
Optimal Interconnections in the Design of Microprocessors and Digital Systems · IEEE Trans. Computers 1980
Electronic design automation › high-level synthesis › data path synthesis
data path allocation
0.011980
Optimal Interconnections in the Design of Microprocessors and Digital Systems · IEEE Trans. Computers 1980

Methods — techniques the papers use, named apart from their topics

switching theory · 0.0minimal covering · 0.0dynamic programming · 0.0microcommand encoding · 0.0bit steering · 0.0
YearPublicationVenuePosition
1981 Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers
abstract
Presents an algorithm for microprogram control memory width minimization with the bit steering technique. The necessary and sufficient conditions to detect the steerability of two mutually exclusive sets of microcommands are established. The algorithm encodes the microcommands of the sets with a bit steering common part and also extends the theory to multiple (more than two) sets of microcommands.
Ayakannu Mathialagan, Nripendra N. Biswas
IEEE Trans. Computers1
1980 Optimal Interconnections in the Design of Microprocessors and Digital Systems
abstract
This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers. These have been called the feasible solutions of the problem. The minimal cost solutions are obtained by assigning weights to the bus-compatible sets present in the feasible solutions. Minimization of the cost of the solution by increasing the number of buses is also discussed.
Ayakannu Mathialagan, Nripendra N. Biswas
IEEE Trans. Computers1