Demo Data from VLDB 2026 / reviewers in the wild / expert
Ponnarasu Shanmugam
dblp:60/6121
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 33% Processor architecture and microarchitecture · 33% Parallel and multicore computing · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.0 | 1 | 1995 | Design of Cache Memories for Multi-Threaded Dataflow Architecture · ISCA 1995 |
Processor architecture and microarchitecture
dataflow architecture |
0.0 | 1 | 1995 | Design of Cache Memories for Multi-Threaded Dataflow Architecture · ISCA 1995 |
Parallel and multicore computing › speculative parallelization
data-triggered threads |
0.0 | 1 | 1995 | Design of Cache Memories for Multi-Threaded Dataflow Architecture · ISCA 1995 |
Methods — techniques the papers use, named apart from their topics
benchmark evaluation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | Design of Cache Memories for Multi-Threaded Dataflow ArchitectureabstractCache memories have proven their effectiveness in the von Neumann architecture when localities of reference govern the execution loci of programs. A pure dataflow program, in contrast, contains no locality of reference since the execution sequence is enforced only by the availability of arguments. Instruction locality may be enhanced if, dataflow programs are reordered. Enhancing the locality of data references in the dataflow architecture is a more challenging problem. In this paper we report our approaches to the design of instruction, data (operand) and I-Structure cache memories using the Explicit Token Store (ETS) model of dataflow systems. We will present the performance results obtained using various benchmark programs. Krishna M. Kavi, Ali R. Hurson, Phenil Patadia, Elizabeth Abraham, Ponnarasu Shanmugam |
ISCA | 5 |