Machine Type Communications (MTC) is one of the major drivers for the future growth of the Third Generation Partnership Project (3GPP) Long Term Evolution (LTE)/LTE-Advanced (LTE-A) standards. A primary challenge associated with MTC using LTE/LTE-A is to cater to varied requirements of the User Equipment (UE) like coverage enhancement, low complexity, low power consumption, etc. The current LTE/LTE-A standards incorporate the Discontinuous Reception (DRX) mechanism for reduced energy consumption where the UE wakes up periodically to check for a paging message from the base-station. On each wake-up occasion, the UE has to decode the paging information, which requires accurate timing resynchronization. In the case of the MTC UEs, especially when the devices are deployed in low coverage areas, the resynchronization consumes a significant amount of time which increases the ON time of the UE leading to higher energy consumption. In this paper, we introduce the Enhanced Primary Synchronization Signal (ePSS) within the LTE/LTE-A standardization framework and propose a novel DRX mechanism which uses our ePSS for faster resynchronization and reduced energy consumption. We demonstrate that our mechanisms are more energy efficient than the legacy DRX mechanism for the MTC UEs with coverage enhancement.

The Third Generation Partnership Project (3GPP) has recognized machine-type communications (MTCs) as a vital medium to drive the Internet of Things (IoT). One of the key challenges in MTC is to reduce the energy consumption of the MTC user equipment (UE). Currently, the 3GPP Long Term Evolution (LTE)/LTE-advanced (LTE-A) standards incorporate discontinuous reception (DRX) mechanism for this purpose. In this paper, we propose a modified DRX mechanism incorporating the quick sleeping indication (QSI) as a novel, simple, and energy-efficient solution for low-complexity, low-mobility MTC UEs. We demonstrate our QSI transmission mechanisms using the broadcast and synchronization channels of LTE/LTE-A for MTC UEs in normal coverage and using the data channel for MTC UEs operating in “coverage enhancement” (CE) mode. For MTC UEs in normal coverage, our simulation results and analysis show that our DRX with QSI mechanisms result in 45% improvement in the energy efficiency and 66% reduction in the computational complexity at the UE receiver, when compared to the current DRX mechanism. For MTC UEs with CE, the energy and computational efficiency increase to 63% and 68%, respectively.

As the instruction issue width of superscalar processors increases, instruction fetch bandwidth requirements will also increase. It will eventually become necessary to fetch multiple basic blocks per clock cycle. Conventional instruction caches hinder this effort because long instruction sequences are not always in contiguous cache locations. Trace caches overcome this limitation by caching traces of the dynamic instruction stream, so instructions that are otherwise noncontiguous appear contiguous. In this paper, we present and evaluate a microarchitecture incorporating a trace cache. The microarchitecture provides high instruction fetch bandwidth with low latency by explicitly sequencing through the program at the higher level of traces, both in terms of (1) control flow prediction acid (2) instruction supply. For the SPEC95 integer benchmarks, trace-level sequencing improves performance from 15 percent to 35 percent over an otherwise equally sophisticated, but contiguous, multiple-block fetch mechanism. Most of this performance improvement is due to the trace cache. However, for one benchmark whose performance is limited by branch mispredictions, the performance gain is almost entirely due to improved prediction accuracy.

The multiscalar architecture executes a single sequential program following multiple flows of control. In the multiscalar hardware, a global sequencer with help from the compiler takes large steps through the program's control flow graph (CFG) speculatively, starting a new thread of control (task) at each step. This is inter-task control flow speculation. Within a task, traditional control flow speculation is used to extract instruction level parallelism. This is intra-task control flow speculation. This paper focuses on mechanisms to implement inter-task control flow speculation (task prediction) in a multi-scalar implementation. This form of speculation has fundamental differences from traditional branch prediction. We look in detail at the issues of prediction automata, history generation and target buffers. We present implementations in each of these areas that offer good accuracy, size and performance characteristics.

As the issue width of superscalar processors is increased, instruction fetch bandwidth requirements will also increase. It will become necessary to fetch multiple basic blocks per cycle. Conventional instruction caches hinder this effort because long instruction sequences are not always in contiguous cache locations. We propose supplementing the conventional instruction cache with a trace cache. This structure caches traces of the dynamic instruction stream, so instructions that are otherwise noncontiguous appear contiguous. For the Instruction Benchmark Suite (IBS) and SPEC92 integer benchmarks, a 4 kilobyte trace cache improves performance on average by 28% over conventional sequential fetching. Further it is shown that the trace cache's efficient, low latency approach enables it to outperform more complex mechanisms that work solely out of the instruction cache.