Demo Data from VLDB 2026 / reviewers in the wild / expert
Sigurd Waaben
dblp:60/6382
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1968
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › magnetic memory
plated-wire memory |
0.0 | 2 | 1968 | High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System · IEEE Trans. Computers 1968 High-Speed Plated-Wire Memory System · IEEE Trans. Electron. Comput. 1967 |
Memory systems › memory architecture
high-speed memory system design |
0.0 | 2 | 1968 | High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System · IEEE Trans. Computers 1968 High-Speed Plated-Wire Memory System · IEEE Trans. Electron. Comput. 1967 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1968 | High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory SystemabstractAbstract—A 1024-word by 80-digit exploratory plated-wire store using diode-matrix word selection has a cycle time of 100 ns or less for READ and 140 ns for WRITE, while the destructive READWRITE asts 150 to 200 ns. To match the fluctuation in the type of request encountered, typically 80 percent READ, and thus maximize the throughput, it is advantageous to switch memory mode in an interlaced manner at logic speed. This is done by exploiting the plated-wire properties of NDRO and fast WRITE. A charge storage diode is used for memory protection and common word current control; READ 400 mA, WRITE 900 mA. Sigurd Waaben |
IEEE Trans. Computers | 1 |
| 1967 | High-Speed Plated-Wire Memory SystemabstractThe plated-wire memory, combined with functional circuit integration, is a strong contender for economic, high-speed, large-capacity memory systems. Important attributes of the plated-wire memory are high-speed DRO and NDRO capability, low digit WRITE current, high output sense signal and low word-to-digit line crosspoint capacitance. Design and operational results for a 1024-word by 80-bit store model are reported in detail. Utilizing a transformerless diode matrix for high-speed word selection, an access time of 75 ns and a READ-WRITE cycle time of 150 ns have been realized. Sigurd Waaben |
IEEE Trans. Electron. Comput. | 1 |