Boolean Satisfiability (SAT), an NP-complete problem central to EDA and AI, has motivated hardware acceleration to overcome its exponential complexity. Early approaches focused on speeding up incomplete solvers, but their inherent algorithmic limitations made them unsuitable for correctness-critical tasks. Consequently, the focus shifted to hardware accelerators for complete solvers based on the DPLL/CDCL framework, which concentrated on accelerating the primary bottleneck: the Boolean Constraint Propagation (BCP) operation. However, performance is ultimately dominated by branching heuristics. Existing designs either omit heuristics, suffering large penalties, or offload them to CPUs, incurring prohibitive overhead. This work presents Heuristic-in-Macro (HiM), the first fully autonomous SAT accelerator integrating both an efficient BCP engine and a hardware-embedded MOMs branching heuristic in a single macro, eliminating CPU dependence. A high-throughput parallel processing architecture replaces traditional serialized clause scans with a tiled multi-macro execution, achieving 8.78× acceleration. At the circuit level, physical efficiency is enhanced through a compact 16T unit cell that merges logic and storage, thereby reducing area and energy. Proposed HiM-based solver achieves 100% SAT/UNSAT solvability, 172.1× speedup in algorithmic performance compared to designs without heuristics. When matched against a CPU-offloaded hybrid system, HiM is 305.6× faster and 1.99×106× more energy-efficient. Compared to the widely used MiniSAT software solver, HiM delivers 26.7× speedup and 3.09×106× efficiency, while reducing time- and energy-to-solution by up to 94% and 83% versus state-of-the-art ASIC accelerators.

Growing demand to deepen understanding of the human brain has accelerated efforts to identify the structure of biological neural networks from neuronal activities. This paper presents a fully digital, tile-able neural array integrated circuit(IC) that, to our knowledge, is the first hardware platform for network reconstruction—inferring synaptic connectivity directly from spike-train data generated by a biological (ground-truth) network. Designed with the overarching goal of emulation of biological networks, the architecture employs repeatable digital neuron-module tiles to ensure the scalability, flexibility and verifiability. Two chip-level run-time interfaces are integrated: a writable spike-forcing path for injecting biological spike pulses into selected IC neurons for synchronized co-firing, and a dedicated monitoring path for streaming spike events, synaptic weights, and membrane potentials. Scalability is further enabled by single-timer Δt capture and a piecewise-linear STDP Δw generator shared per neuron, avoiding complex LUTs/multipliers while preserving biological plausibility. The platform is realized in silicon and tested with an FPGA-based setup. Using only spike activity, the system reconstructs synaptic connectivity with high fidelity across diverse ground-truth networks ranging from simple 2-layer topologies to biologically derived C.elegans head network, as well as networks with bimodal and trimodal weight distributions. Accuracy was comprehensively quantified from multiple perspectives for both connectivity and spike-train similarity, confirming faithful replication. These results demonstrate that the proposed platform can recover the synaptic structure from spikes alone and provide a practical tool for predicting network learning responses under varied stimuli, advancing biological neural network research and real-time neuromorphic experimentation.

This paper presents a 6.78-MHz inductive wireless power transfer (WPT) system designed for implantable medical devices (IMDs). To meet the stringent IMD limits on form factor, power conversion efficiency (PCE), and regulation, the proposed system adopts a resonant current-mode (RCM) method. A compact RX coil, under spatial constraints, necessitates the adoption of the RCM method, which provides a voltage conversion ratio greater than unity, enabling efficient transfer of the energy stored in the LC tank to the output. To achieve high regulation performance, a deficit-energy-quantifying (DEQ) resonant regulating rectifier (3R) is introduced. The DEQ-3R operates by quantifying the energy deficit to reach the target output voltage and comparing it with the LC-tank energy. Comparison result detects the transition timing from the resonance phase to the charging phase with a delay-compensated comparator (DCC) adaptive to the LC-tank energy level. The proposed DEQ-3R is implemented in a 180-nm CMOS process, occupying 1.04 mm2 active area. Experiment results using an 80-nH RX coil demonstrate regulated 2.5-V operation over a coupling-coefficient range of 0.1-0.16 and a load power range of 5-45 mW. The prototype achieves a peak PCE of 81.28%, reflecting a 6.08% improvement over a counterpart without the DEQ, while reducing the VOUT ripple from 432mVPP to 168mVPP with a 20-nF output capacitor.

A novel reference search algorithm is proposed in this paper to significantly reduce the reference search time of embedded spin transfer torque magnetic random access memory (STT-MRAM). Unlike conventional methods that sequentially search reference levels with linearly increasing references the proposed Dual Read Reference Search (DRRS) algorithm requires only two array read operations. By analyzing the statistical characteristics of the read data using a customized function the optimal reference level can be quickly determined in a few steps. Consequently the number of read operations required for a reference search is reduced providing a substantial improvement in the reference search time. The DRRS algorithm can be operated on-chip its effectiveness was confirmed through simulations. The optimization speed was improved by 85% compared to the conventional methods. Additionally an Triple Read Reference Search (TRRS) algorithm is proposed to decrease the variation occurring across different cell arrays and to enhance optimization accuracy. STT-MRAM is composed of numerous cell arrays where the cell distributions in each array exhibit different characteristics. The TRRS algorithm enhances optimization accuracy for variations occurring in each array achieving over a 2x increase in accuracy compared to the DRRS algorithm. Furthermore Simultaneous Reference Search for P and AP (SRS) algorithm that significantly reduces the search time by simultaneously optimizing Parallel (P) and Anti-parallel state (AP) reference cells is also proposed. Lastly regarding cell degradation after power-up we enable prompt re-optimization through revolutionary time-saving algorithms (DRRS TRRS and SRS). This allows for rapid re-optimization in the event of errors caused by cell degradation and ensures regular optimization to maintain maximum read margin even before errors occur thereby enhancing reliability.

A novel Resistive random access memory (ReRAM)-based Compute-in-memory (CIM) macro is proposed to overcome the limited accuracy and throughput of a conventional ReRAM-based CIM macro that results from to the low R-Ratio and large variation of ReRAM. The proposed structure consists of 1T2R1C bit-cells and 4-kb ReRAM-based nvCIM architecture with ternary weight and ternary input. Ternary multiplication is implemented with voltage division between paired ReRAM devices within a bit-cell to make the output voltage variation tolerant and less sensitive to low R-ratios. An accumulation operation is realized with capacitive coupling so that linearity can be guaranteed for a large number of operands, allowing accurate and fast multiply-and-accumulate (MAC) operations. For comprehensive validation of the proposed CIM macro, the Verilog-A models for ReRAM devices with an adjustable R-ratio and adjustable variations are adopted to perform simulation on various R-ratio and variation conditions. With the peripheral circuits designed in 180-nm CMOS technology, the proposed CIM macro is confirmed to have high variation tolerance, high throughput, and less sensitivity to a low R-ratio, resulting in a high ternary DNN accuracy of 99.07% (0.01% drop) for the MNIST and 83.79% (0.38% drop) for the CIFAR-10 data sets with an R-ratio as low as 38 and 20%/40% low/high resistance variation.

An energy-harvesting interface that incorporates a continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) dc-dc converter with maximum power point tracking (MPPT) is introduced in this paper. By exploiting unique characteristics of a CSCR SC converter, an MPPT based on the hill climbing algorithm is implemented with a real-time power monitoring scheme with a frequency-mapped sampling capacitor DAC, allowing variation-tolerant MPPT for various types of energy sources. The harvestable voltage range is significantly extended by a step-up/down convertible CSCR SC converter, and the voltage conversion efficiency is further improved with matrix-structured and load-mapped power switches. With the test chip fabricated in 28nm FDSOI technology, the proposed energy harvesting interface shows peak conversion efficiency of 89% and average efficiency of > 80% for 60-2,$794~\mu \text{W}$. MPPT efficiency of > 97 % is confirmed with energy harvesting measurement with a solar cell.

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8-b weight to 119.2 TOPS/W for 2-b weight.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

Wireless sensor nodes (WSNs) are essential elements for today's structural health monitoring (SHM). As the design technology for WSNs evolves, there have been continuous efforts to address challenges for WSNs such as short lifetime, high power consumption, and bulky volume. Recent trends show energy harvesting becoming a popular solution for extending the lifetime of WSNs; even implementing energy-autonomous systems is an option. Smaller WSN form factors have been developed for volume-limited applications and sensor nodes as small as a few mm3were created with custom-designed integrated circuits (ICs). Custom IC-based sensor nodes enable energy-efficient implementation of WSNs for SHM. Ultralow power circuits with operation power on the order of nanowatts are introduced in this paper. Ultralow power energy harvesters, timers, wakeup receivers, sensing modalities, and microprocessors are expected to significantly extend sensor node lifetime or achieve sensor node operation with ambient energy harvesting.

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.

An ARM-based sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. The ultra-low power chip featuring an ARM Cortex-M0 processor, 3kB of SRAM, and power management unit (PMU) with energy harvesting from MFCs is designed to consume 11nW in sleep mode for perpetual sensing operation. A small-scale micro-MFC with 21.3cm2anode surface area was connected to the on-chip PMU to charge a thin film battery of 1mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1 sec wake-up time demonstrated the sustainability of chip-on-mud concept. During sleep mode, the system charges the 4V battery at 380nA from the micro-MFC generating 5.4μW of power, which can support up to 20mA of active mode current.

We present a self-adapting power management unit (PMU) for ultra-low power wireless sensor nodes. The PMU uses 1.03nF of on-chip MIM capacitance in a reconfigurable switched-capacitor network (SCN) that automatically adapts to different battery voltages for down-conversion and different harvesting sources/harvesting conditions for up-conversion. The PMU achieves 63.8% / 60.7% down-conversion efficiency at 17.9μW active mode / 12.8nW sleep mode power loading. With the adaptive down-conversion ratio, load power range is improved by 3.76× and 5.48× in sleep and active mode, respectively. We show how the proposed adaptation method enables harvesting with solar, microbial fuel cell, and thermal energy sources, increases harvesting efficiency by 1.92× and achieves the peak extraction efficiency of 99.8% for solar cell.

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.

Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.

In this work we expose the challenges of interfacing both conventional and new systems with an extremely resource constrained platform. We find that even when attempts are made to utilize an industry standard protocol (I2C), necessary protocol modifications for ultra-low power design means that interfacing remains non-trivial.

The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade. Device characteristics as determined through Technology Computer Aided Design (TCAD) tools are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that a HETT-based ring oscillator (RO) shows a 9−19X reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional MOSFETs, namely asymmetric current flow and increased Miller capacitance, analyzing their effect on circuit behavior and proposing methods to address them. Finally, HETT characteristics have the most dramatic impact on SRAM operation and hence we propose a novel 7-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7−37X reduction in leakage power compared to CMOS.