High-level modeling for operational amplifiers (opamps) has been previously carried out successfully using models generated by published automated model generation approaches. Furthermore, high-level fault modeling (HLFM) has been shown to work reasonably well using manually designed fault models. However, no evidence shows that published automated model generation approaches based on opamps have been used in HLFM. This paper describes HLFM for analog circuits using an adaptive self-tuning algorithm called multiple model generation system using delta. The generation algorithms and simulation models were written in MATLAB and the hardware description language VHDL-AMS, respectively. The properties of these self-tuning algorithms were investigated by modeling complementary metal-oxide-semiconductor opamps, and comparing simulations using the HLFM against those of the original simulation program with integrated circuit emphasis circuit utilizing transient analysis. Results show that the models can handle both linear and nonlinear fault situations with better accuracy than previously published HLFMs.

Automatic approaches for macromodel generation from SPICE-level descriptions have been of great interest over the last few years for the design of large, complex mix- signal SoCs (system-on-chips) and SiPs (system-in-packages). In this paper a novel approach termed multiple model generation system (MMGS) is developed for extracting either single-input single-output (SISO) or multiple-input single-output (MISO) macromodels from a SPICE netlist. This model generation process detects nonlinearity through variations in output error. Examples of the application of MMGS are presented for simple two-input systems incorporating a two-stage CMOS operational amplifier (op amp).

Microgrid CMPs, that is based on microthreaded processors, use hardware scheduling and synchronisation and have structures to support this that are distributed, fully scalable and which can support hundreds of microthreads per processor and their associated microcontexts. The chip has locality in communication wherever possible, and supports a globally-asynchronous locally-synchronous (GALS) design approach, where all its global communications are asynchronous, creating independent clocking domains for each microthreaded processor. Each microthreaded processor has its own instruction window and local register file, both of which are fully scalable. Any remote access is fully decupled from the pipeline operations including memory. This paper introduces the microgrid CMP architecture model and discusses in general terms how our approach meets the challenges facing CMP architectures. It also summarizes microgrid CMP performance simulations published elsewhere and presents a local scheduler and the microthreaded in-order pipeline.

We describe a CMOS on-line-self-testing, double-sampled, fully-balanced, switched-current bilinear integrator. High spot-defect fault coverage of the integrator, clock generator and checking circuit is achieved under normal process variations.

CMOS operational amplifier transistors containing a single gate oxide short (GOS) fault between the source and drain were diagnosed from SPICE simulations of the supply current responses to ramp and sinusoidal test stimuli. Multilayer perceptron (MLP) artificial neural networks were trained to classify the faulty transistors from the responses. Functional testing did not always reveal the GOSs so this method offers reliability testing against future failure since the GOSs can deteriorate during operation of the circuit. The GOSs were modeled by a diode and series resistance at various distances from the source. The breakdown voltages of the model diode significantly affected the responses and diagnostic accuracies. If they are in the expected practical range (/spl les/2 V) and are uniform in value, then by combining test results from both stimuli, accuracies of 100% are obtainable. If their values are variable or higher, the accuracies decrease, and the test reduces to a go/no go test. No test pins are required so the method is applicable to any circuit.

This paper considers the implications of structural test for analog and mixed signal (analog and digital) circuits and describes fault simulation software suitable for investigating a variety of test methods. Results from simulation investigations of dynamic supply current test are presented and compared with results obtained for real circuits. In both cases the results indicate increased fault coverage and reliability benefits. The dynamic supply current monitoring equipment used to implement the hardware test is described.

This article presents a new concept for concurrent self test of switched current circuits based on S/sup 2/I cells as basic building blocks. Six different transistor faults were modelled and the ability to detect the various fault-situations was studied. The fault detection system presented was applied to a simple switched-current integrator in which all the different faults were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be realised with a minimum of additional overhead circuitry.