This work presents a time register designed for time-domain signal processing, employing a delay line in a ring configuration topology combined with a digital counter to achieve a high dynamic range. The proposed architecture supports both addition and subtraction operations, offering a practical framework for understanding the implementation of such functionalities in the time domain. The register is capable of efficiently processing signals with durations ranging from picoseconds to milliseconds and demonstrating feasibility for physical implementation.

This paper introduces a novel time register for time-domain signal processing, utilizing a delay line within a ring configuration topology and a digital counter to achieve high dynamic range. The proposed design was implemented and simulated using the AMS 350 nm CMOS process and tested under nominal supply voltage of 3.3 V. Corner simulation, considering supply voltage, temperature, and process variations, demonstrated an error rate below 2% for inputs exceeding 50 ns. A key advantage of the proposed solution is that its range can be easily scaled by increasing the number of counter bits, while the layout area overhead introduced by the counter remains minimal. This is the first CMOS time register capable of efficiently processing signals from picoseconds to milliseconds, providing an output pulse equal to the input pulse, and being feasible for physical implementation.

We introduce a novel soft-decision decoding algorithm for binary block codes named ordered reliability direct error pattern testing (ORDEPT). The proposed technique tests a list of partial error patterns (PEP)s that are arranged according to their logistic weight and completed on-the-fly based on the instantaneous received sequence and the code’s parity-check matrix. Our results, obtained for a variety of popular short high-rate codes, demonstrate that ORDEPT outperforms state-of-the-art decoding algorithms such as ordered reliability bits guessing random additive noise decoding (ORBGRAND) in terms of decoding complexity, and is hardware-favorable in terms of latency and energy consumption. The improvements carry on to the iterative decoding of product codes and convolutional product-like codes, where ORDEPT demonstrates the ability to efficiently find multiple candidate codewords and outperform state-of-the art competitors.

This article presents a 10-bit radiation-hardened-by-design (RHBD) SAR analog-to-digital converter (ADC) operating at 50 MS/s, designed for aerospace applications in high-radiation environments. The system- and circuit-level redundancy techniques are implemented to mitigate radiation-induced errors and metastability. A novel split coarse/fine asynchronous SAR ADC architecture is proposed to provide system-level redundancy. At circuits level, single-event effects (SEEs) error detection and radiation-hardened techniques are implemented. Our co-designed SEE error detection scheme includes last-bit-cycle (LBC) detection following the LSB cycle and metastability detection (MD) via a ramp generator with a threshold trigger. This approach detects and corrects radiation-induced errors using a coarse/fine redundant algorithm. The radiation-hardened latch comparators and D flip-flops (DFFs) are incorporated to further mitigate SEEs. The prototype design is fabricated using TSMC 65-nm technology, with an ADC core area of 0.0875 mm2and a power consumption of 2.79 mW at a 1.2-V power supply. Postirradiation tests confirm functionality up to 100-krad(Si) total ionizing dose (TID) and demonstrate over 90% suppression of large SEE under laser testing.

This article presents a novel time-domain implementation of the second-order Goertzel frequency analyzer, which can be extended for use in infinite impulse response (IIR)/finite impulse response (FIR) filters. A set of time-domain arithmetic circuits, including a one-step time register (TR), time amplifier (TA), time adder, and unit delay operator (${z}^{-1}$), are introduced to overcome the limitations of conventional time-domain filters. The working principles and nonidealities of each block are analyzed and compared with the existing methods. The proposed filter is implemented in a 180-nm CMOS process with a 0.9-V supply voltage. The designed frequency analyzer is tunable to extract the amplitude and phase angle of signals up to 400 Hz. Simulation results, targeting a 280-Hz signal at a 19.88-kHz sampling frequency, demonstrate that the filter can detect the amplitude and phase of a voltage signal in the time domain with an error below 5%. The filter achieves a resolution of$76.7~\text {dBV/s}$, consumes less than$24~\mu \text {W}$of power, and the estimated silicon area is almost$0.828~\mathrm {mm}^{2}$.

This brief presents an open-loop current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) intended for ultralow power direct digitizing micro-sensors readout applications. The proposed highly linearized pseudo-differential${G}_{M}$-stage mitigates the harmonic distortions induced by the tune circuit to the nonlinear transfer characteristic of the voltage-controlled oscillator (VCO), and it improves the total SNDR considerably. The ADC is implemented in 180-nm CMOS and achieves a peak SFDR of 81.48 dB, THD of −76.8 dB, and SNDR of 70.9 dB (equivalent to 11.48 ENOB) over a 3.6 kHz bandwidth with a 110 mVPP input differential sinewave. A chopper is used for the input transconductance stage to mitigate the input-referred noise and its impact on output phase noise. The ADC consumes$20.3 \mu {\text {W}}$from a 1-V supply.

In this work we introduce a novel soft-decision decoding algorithm for high-rate short error-correction codes. Our results demonstrate that the proposed algorithm improves over the state-of-the-art algorithms, including recently proposed Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND), in terms of latency and decoding complexity. Specifically, we demonstrate that the ability of the proposed algorithm to find multiple candidate codewords with a reduced number of low-complexity queries makes it an efficient component decoder for iterative decoding of product-like codes.

This paper presents a high-speed low dropout (LDO) regulator with wide dynamic range. The use of piecewise speed enhancement technique dividing the loop dynamic into three phases in which the current regulation circuits (CRC), large-signal derivative path control circuits addressing the design challenge of slew rate limitation, and the hybrid passive-active frequency compensation (PAFC) for small signal settling time improvements are introduced lends the proposed LDO to providing constant output voltage under the condition of large load variations. The LDO is designed in TSMC 180-nm 1.8 V standard CMOS technology with 0.17 mm2 active area. The quiescent current is 380$\mu \mathrm{A}$at no load. With regulated 1.2 V output, the input voltage ranges from 1.3 V to 1.8 V. The measured overshoot and undershoot with load steps of 0 to 100 mA at 50 ns edge time are 135 mV and 105 mV, respectively. The settling time at 25 mA, 50 mA and 100 mA are 2.6$\mu \mathrm{s}, 4.5\mu \mathrm{s}$, and 9.8$\mu \mathrm{s}$, respectively. The LDO is competent in handling a wide range of output capacitance from 0 to 5 nF while the overshoot and undershoot exhibits small variation in the load step response.

Existing methods used for the clock distribution of multiple dies employ a balanced tree structure to minimize the impact of the within-die process and loading variations. No topology for die-to-die clock skew compensation of more than two dies has been presented yet. This article presents a novel die-to-die clock skew compensation topology to address these limitations. Unlike existing designs, the proposed topology does not need a phase detector (hence, no dead zone); it only requires one through-silicon via (TSV) to connect a pair of dies and one digitally controlled delay line (DCDL) in each die; thus, there is no skew from extra TSVs and DCDLs. Accordingly, the system has a small chip area and low lock time. The postsynthesis of this work was accomplished in a 65-nm CMOS process. The performance of our design was evaluated theoretically and practically in terms of mismatch/finite resolution of delay lines, buffer mismatch, and TSV delay. Under identical conditions, the residual skew of the proposed design was as low as 13 ps at 1 GHz. This study is the first to obtain the solution for die-to-die clock synchronization of multiple dies (more than two dies) in a three-dimensional (3-D) integrated circuit, while other systems can only support two dies.

In this article, a novel approach for performing multiply–accumulate (MAC) operations in the time-domain is presented. The Internet of Things, machine learning, and 5G are driving up demand for this type of operation, which is also crucial for many applications that rely on digital signal processing (DSP). For accomplishing this operation, a fully time-domain MAC unit capable of consecutively multiplying two input time pulses and adding them to previously stored signals is proposed. The main component of the circuit is the time register, which adds and stores time information. The MAC unit design is realized in commercial 180-nm CMOS process and occupies an estimated area of about$3167 \mu \text{m} ^{\mathrm{ 2}}$. The proposed circuit can perform MAC operations with less than 5% error for a dynamic range (DR) of 19 ns, presenting an$R ^{\mathrm{ 2}}$linearity of over 0.99. Its power consumption is 1.72 mW from a 1.8-V supply.

This work presents an automated design methodology for time-mode proportional and integral (PI) controllers aimed for an on-chip switched-capacitor (SC) dc/dc converter system. The basis of this design is the use of evolutionary optimization algorithms to find the near-optimal set of sizings for the time-mode PI controller. It is motivated due to the difficulty faced when tuning the controller parameters at a circuit level, which arise as a result of the presence of modeling inaccuracies and the small region for the linearized model where it is defined. Moreover, this design proposes the required modifications for the original design presented for the inductor-based dc/dc converter. These modifications are necessary to operate the SC dc/dc converter in slow switching limit (SSL). The addition of a pulse-width-modulated (PWM)-to-pulse frequency-modulated (PFM) conversion block is presented and elaborated in this article. The controller is codesigned using the differential evolution algorithm for the circuit level implementation to mitigate the issues prior mentioned. The optimized controller is then tested in a simulation environment using TSMC$0.18~\mu \text{m}$technology. The results of the optimized controller were superior to those of a conventional controller. The optimized system achieved an overall efficiency of 79.1%.

This brief presents a power and memory-optimized hardware implementation for the open forward error correction (oFEC) encoder proposed for high-speed fiber optical communications. Instead of storing a large amount of previously encoded data in the memory as suggested in oFEC proposal, we propose an alternative algorithm that requires the knowledge of only a few blocks of preencoded partial parity-check bits with the goal to reduce circuit power consumption. We then present a hardware implementation architecture for both the standard and optimized encoding algorithms and demonstrate that power dissipation and area overhead are reduced multiple times by optimized implementation.

Operational transconductance amplifiers (OTAs) are widely employed as active elements in filters, data converters, and buffer amplifiers. Inverter-based implementation of OTAs is an attractive approach for low voltage realization of analog subsystems. However, there are still fundamental challenges such as how to simultaneously achieve high DC gain, bandwidth, speed, and good noise performance based on existing inverter-based OTA architectures. In this paper, a new two stage OTA, hybrid with current reuse inverter OTA and Nauta transconductor is proposed to improving performance by taking advantages of their own merits. The introduced architecture is keeping the merits of Nauta transconductor such as high bandwidth, high speed and the superior input referred noise performance of the current reuse inverter-based OTA. Furthermore, in order to reduce the PVT variations, bulk tuning circuits based on "detecting-feedback" loop applied on CMFB and the output stage of Nauta transconductor is proposed to dynamically tune the output DC levels under PVT variations. The proposed new hybrid OTA is implemented in 180nm CMOS technology and achieves very competitive performance compares with all inverter based OTAs and the other state-of-the-art OTAs.

A type-II analog phase-locked loop without charge pump and analog loop filter is proposed in this paper. A novel discrete proportional-integral-derivative circuit (DPIDC) is proposed to implement phase error integration and frequency compensation with time-domain processing. A phase-to-voltage converter (PVC) with a sample-and-hold is used to convert the phase error processed by the DPIDC to a voltage that controls the voltage-controlled oscillator (VCO). Simulation results in 180nm CMOS technology show the proposed DPIDC and PVC circuits only consume 6.5-μW power at 0.6-V supply voltage. The proposed PLL settles down steadily and achieves a normalized reference-spur rejection better than -84.6dBc.

We focus on a hardware implementation of the concatenated forward error-correction (FEC) decoder defined in 400ZR implementation agreement to provide a throughput of 400 Gbps over fiber-optical communication links. We propose a soft-input hard-output low-complexity decoding algorithm for the inner Hamming code. We demonstrate that the algorithm leads to an efficient hardware design with low silicon area and power dissipation. We then propose a hardware implementation architecture of the outer staircase decoder. It features a highly optimized low-power implementation of Bose-Chaudhuri-Hocquenghem (BCH) component decoders and the staircase decoder memory that can be efficiently accessed by either vertical or horizontal component decoders. Finally, we analyze the hardware implementation of the entire 400ZR decoder and investigate the trade-off in terms of power, area, and speed, that results from the inner/outer decoder concatenation and is dictated by the bit-error rate at the output of the inner decoder.

In this paper, the concept of utilizing machine learning algorithms for person identification through physical activity is proposed. Many previous machine learning research articles focused on building models to identify physical activities using a sensor fusion input. Nevertheless, there has been no focus on building models that can identify the activity performer as well. This paper will demonstrate that machine learning can be applied not only for the identification of physical activities but also for the identification of the activity performer as well. The paper will present the achieved accuracies for the person identification through physical activities using different machine learning algorithms. Additionally, a novel multi-label shared deep neural network (DNN) is proposed for identifying both the physical activity and the activity performer simultaneously. The proposed design allows for a single training/re-training which is advantageous over having to train two separate DNNs. Moreover, it is 30% smaller compared to a design that consists of two separate DNNs for identifying the physical activity and the activity performer.

This brief presents a VLSI architecture of a high-throughput, low-latency, and power staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and precomputing partial parity bits for the next staircase block while generating the current staircase block. The proposed encoder is designed with a multistage pipelined architecture that enables high efficiency in terms of throughput and area. Using 65-nm CMOS technology, the synthesized encoder achieves 432 Gb/s when operating at 909 MHz, with the power consumption of 323 mW.

High Efficiency Video Coding (HEVC) encryption, which has been proposed to encrypt intra prediction modes (structural information), transform coefficients (texture information), and motion related codewords (motion information), has received considerable attention recently. However, there is still the issue of efficiency when HEVC encryption is applied in the Internet of Multimedia Things (IoMT). Aiming at this challenge, in this paper, we propose a new low-overhead HEVC encryption scheme for energy-constrained IoMT. Concretely, the proposed scheme adjusts the selection of the aforementioned syntax elements to be encrypted according to the structure, texture, and motion energy present in each frame. It works as follows. The energy levels of quantized coefficients and motion vectors are calculated and compared with adaptive threshold values to classify the energy level in each video frame. When there is a high energy frame in the video, all the syntax elements are encrypted. When there is a low energy frame, alternate syntax elements are encrypted for achieving low encryption overhead. Moreover, in the case of transform coefficients, to withstand the interpolation attack, alternate coefficients are encrypted after correlating the frame with its neighboring coefficients. Extensive experiments were conducted, and the results demonstrate that the proposed scheme efficiently reduces the encryption overhead with low impact on the security level, making it suitable for IoMT.

This brief presents an on-chip autotuning algorithm to reduce the supply voltage sensitivity of digitally controlled delay lines constructed using identical digital buffers. The proposed algorithm tunes a compensator circuit embedded within each buffer to counterbalance the supply sensitivity of the overall delay line regardless of process or mismatch variations. A 3-D IC mismatch-insensitive skew compensation (MISC) architecture employing this delay line is fabricated in 65-nm CMOS and demonstrates robust performance against the buffer supply noise at operating frequencies of 250 MHz to 1 GHz. The rms jitter of this supply-compensated MISC design measures 3 ps in the presence of a 25-mV 1-MHz supply noise at 1-GHz operation, compared to 112.3 ps for the conventional design, whereas the maximum residual skew between the Die-1 and Die-2 clocks measures under 30 ps across the entire MISC frequency range.

A linearization technique of voltage-to-frequency characteristics of voltage-controlled oscillator (VCO) analog-to-digital converters (ADCs) is presented. In contrast to previous works, the proposed technique is an open-loop calibration-free configuration, so it can operate at higher frequencies. It is also independent of the delay element structure, so it can be applied to various VCO ADC topologies. The analog input signal is first mapped through a preweighted resistor network in which every delay element experiences a different version of the input and produces the corresponding delay. As a result, the proposed approach suppresses the impact of V/F nonlinearity on the ADC performance by expanding a linear region of the transfer curve over the full rail-to-rail input. This technique shows substantial improvement results by keeping nonlinearity within ±0.5% over the full input scale (dBFS) and achieves a peak signal-to-noise and distortion ratio (SNDR) of 75.7 and 60.4 dB for input of -8 and 0 dBFS, respectively.

Traditional die-to-die (DTD) clock skew compensation topologies prerequisite matched delay lines or equal through-silicon via (TSV) delays. Unlike previous techniques, the proposed mismatch-insensitive skew compensation architecture can maintain a synchronous clock signal between two dies, while completely eliminating any skew arising from code-dependent mismatch in delay lines or unequal TSV delays. The performance of our design is verified in theory and simulation in light of mismatch/finite resolution of delay lines, clock jitter, phase detector dead zone, TSV delay, and buffer mismatch. Postsynthesis timing verification of this cell-based design was done in a 65-nm CMOS process. Under similar worse case mismatch conditions, the residual skew in the proposed architecture was delimited to 32 ps at 1 GHz, compared with 116 ps for a recent DTD topology, while consuming only 2.1 mW.

This paper presents a high efficient multi-stages full-wave RF to DC rectifier for RFID applications. The proposed converter employs diode-connected transistors with gate to drain bootstrapping capacitor to overcome threshold drop of voltage. Rectifying transistors are biased in triode region to improve the driving capability of the circuit while they operate at lower input voltages. Bulk biasing technique is applied to ensure faster turn on for level shifting transistors. Simulation results in 90nm CMOS technology at frequency of 920MHz, show that output voltage and power conversion efficiency at low input power level are improved compare to conventional rectifier using diode-connected transistors.

A bandgap reference with curvature corrected compensation which utilizes the subtraction of currents generated from complementary NMOS and PMOS bandgaps using MOS transistors in subthreshold is presented. A transimpedance amplifier with accurate input current compensation is used to overcome the problems due to input common range limitations of operational amplifiers. The bandgap reference uses power supply of 0.8V, the accuracy is 19ppm/K for 386mV in the temperature range of 0 to 130C. The PSRR is 24dB for 1kHz and 23dB for 10kHz.

This paper presents an efficient low power protection technique for thin gate oxide of DMOS transistors. By connecting a capacitive divider structure to the floating gate node of a DMOS transistor, its effective gate oxide thickness is increased, and a protection from breakdown due to high voltages (HV) applied to its gate is achieved. Several HV circuits, including: positive voltage doubler and level-up shifter suitable for ultrasound sensing systems are built successfully around this technique. These circuits were implemented with the 0.8 μm CMOS/DMOS HV DALSA process. Experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 120V.