Deep neural networks (DNNs) have been increasingly deployed on edge devices, enabling edge-intelligent applications. However, this introduces significant security vulnerabilities, especially the degradation of network performance caused by external attacks such as bit-flip attacks (BFAs). Traditional defense methods based on spatial redundancy, such as triple modular redundancy (TMR), consume a significant amount of hardware resources, and existing fault-aware training (FAT) methods do not significantly improve robustness. To address these issues, we propose an efficient defense method, which combines fault-aware training and spatial redundancy, against BFAs for DNNs. Specifically, a progressive fault-aware training method is proposed to enhance the inherent robustness of DNN models. Subsequently, a JS divergence-guided TMR approach is developed, which identifies a small number of critical weights in the trained model that significantly impact model accuracy by JS divergence analysis and applies TMR only to the critical weights, to further enhance the model’s robustness. The experimental results obtained on the VGG-13/ResNet-20/ResNet-34 models and the CIFAR-10 dataset show that compared with the FAT-type methods, our proposed method improves the robustness of the models by up to $5.6 \times$; compared with the spatial redundancy methods, our method improves the robustness by $1.9 \times$ and reduces memory storage overhead 23% in the experiment platform.

This paper presents a hardware-software co-design for efficient dynamic sparse spectral clustering. We introduce a heterogeneous streaming architecture that replaces dense SVD with a sparse iterative solver. Key contributions include: (1) dynamic graph generation to minimize memory footprint; (2) tile-centric dataflow to maximize sparse matrix reuse; and (3) an INT8 mixed-precision datapath. Implemented on Xilinx VCK190, our design achieves up to 22× speedup and 39× higher energy efficiency than an RTX 3090 GPU.

Abstract: Spectral clustering is powerful but limited by O(N³) complexity. We present CODESCA, a co-design on Xilinx VCK190. By offloading sparse graph construction to the host and utilizing a quantization-aware block power iteration engine on FPGA, CODESCA achieves 22× speedup over CPU and 9× better throughput-per-watt than RTX 3080 GPU, enabling efficient edge data mining.

This is a corrigendum for the article "Unified and Efficient Factor Graph Accelerator Design for Robotic Optimization" published in ACM Trans. Arch. Code Optim. 22, 4, Article 153 (December 2025), 23 pages.

The deployment of large-scale convolutional neural networks (CNNs) on hardware often results in reduced execution efficiency and increased hardware overhead. Prior works have addressed this challenge by employing pruning techniques to reduce parameters and computational loads. Among these techniques, fine-grainedN:Mpruning methods achieve high sparsity rates but at the cost of generating substantial indexing overhead and potential workload imbalance. In contrast, pattern-based pruning methods reduce indexing complexity and achieve workload balancing but suffer from low sparsity. To overcome these limitations, this article proposes a kernel-aware hybrid pruning (KAHP) method that simultaneously attains high sparsity, workload balancing, and reduced indexing overhead. Moreover, to accelerate the inference of the models pruned by the KAHP method, we design an efficient accelerator based on the systolic array architecture. Experimental results demonstrate that, compared to theN:Mpruning method, the KAHP method achieves workload balancing and reduces the number of indices by up to 88.7% on ResNet-20. Compared to pattern-based pruning methods, the KAHP method achieves up to$31.8\times $sparsity. The proposed accelerator achieves up to 93.18 GOPS/W power efficiency and 0.721 GOPS/DSP computation efficiency.

Approximate computation is a method that effectively reduces design complexity and resource consumption of computing systems. Floating-point (FP) multiplication is a computationally complex and resource-intensive operation and is widely used. Therefore, the approximate FP multiplier has been a promising alternative for improving computation efficiency. In this paper, we propose an accuracy-configurable logarithmic FP multiplication algorithm (ACLAM) and design an efficient circuit structure for it. ACLAM simultaneously computes the approximate product and the error of the logarithmic multiplication. Then a part of the error is added to the product to achieve different levels of accuracy. The complexity of the circuit is reduced by approximating the error expression and calculating the error only based on the Most Significant Bits (MSBs) of the mantissas. Experimental results show that, compared to the exact FP multiplier, ACLAM can reduce 88.1% of area, 89.8% of energy, and 28.1% of delay while maintaining an average accuracy of 99.07%. The proposed ACLAM is also applied to two real applications to demonstrate its efficiency and effectiveness.

Embodied AI robots have the potential to fundamentally improve the way human beings live and manufacture.Continued progress in the burgeoning field of using large language models to control robots depends critically on an efficient computing substrate, and this trend is strongly evident in manipulation tasks.In particular, today's computing systems for embodied AI robots for manipulation tasks are designed purely based on the interest of algorithm developers, where robot actions are divided into a discrete frame basis.Such an execution pipeline creates high latency and energy consumption.This paper proposes Corki, an algorithm-architecture co-design framework for real-time embodied AI-powered robotic manipulation applications.We aim to decouple LLM inference, robotic control, and data communication in the embodied AI robots' compute pipeline.Instead of predicting action for one single frame, * equal contribution.

Recently, training deep neural networks (DNNs) on edge devices has attracted much attention due to its strong adaptability and avoidance of private data transmission. However, limited computational, storage, and energy resources pose significant challenges for edge devices. The structural and computational redundancies in DNNs create opportunities for sparse training through model pruning and zero-computation skipping. Although feasible, the sparse training accelerator design encounters common issues, such as redundant data duplication and unbalanced workloads, caused by irregular sparsity. To address these issues, this paper proposes a sparse DNN training accelerator, SDTA, together with a hierarchical pre-fetching buffer and a dynamic scheduler to achieve high design efficiency. The SDTA is deployed on the FPGA XCVU3P platform. Compared to the prior FPGA-based accelerators and the GPU, SDTA improves the energy efficiency by up to 2.29×, the storage utilization efficiency by up to 7.37×, and the computational efficiency by up to 1.9×. Compared to the dense accelerator, it achieves a speedup of up to 5.88×, while ensuring model accuracy.

The rapid development of artificial intelligence raises higher demands on the performance of intelligent devices, requiring new computing units with lower resource usage and power consumption. Approximate Multipliers (AMs) meet this need by reducing resource and power consumption at the cost of computational accuracy and are widely used in fields like image processing and deep neural networks. In this article, we present a Low-Cost and High-Accuracy Approximate Multiplier (LHAM) design methodology targeting Field Programmable Gate Arrays (FPGAs). The expressions of carry propagation and carry generation for FPGA-based Carry-Look-Ahead Adders (CLA) are optimized, which effectively reducing the errors associated with discarding carry generation information. Using these expressions together with a logic fusion based approximation strategy, we design both accurate and approximate adders. These adders can be selectively configured during the partial product accumulation stage of the multiplier, allowing a tunable tradeoff between computational accuracy and hardware resource utilization. Finally, we model the AM design space as a 0-1 Knapsack problem to efficiently generate optimized designs under varying accuracy and area requirements. Experimental results show that, compared to the Xilinx accurate multiplier IP core, the proposed LHAM reduces LUT usage, delay, and power consumption by 50.7%, 21.7%, 20.6% for \(8\times 8\) multiplication, respectively. Compared to existing AMs, LHAM uses the fewest LUTs and achieves the best tradeoff between accuracy and area. The proposed LHAM is also applied to two applications to demonstrate its efficiency and effectiveness.

Convolutional neural networks (CNNs) are widely used in computer vision and natural language processing. Field-programmable gate arrays (FPGAs) are a popular accelerator for CNNs. However, FPGAs are prone to suffer soft errors, so the reliability of FPGA-based CNNs becomes a key problem when used in safety-critical applications. The convolution module based on a processing element (PE) array is the most complex part of the accelerator, so it is the key to efficient protection. Coding-based schemes have been proposed for efficient protection of the convolution module, where the processing of the PE array is modeled as parallel matrix-vector multiplications (MVMs), and every wrong output would be concurrently detected and corrected. However, these schemes cannot deal with errors in the configuration memory that affects many intermediate results. In this article, a protection scheme is proposed based on faulty PE detection and replace (DR) to deal with such configuration memory errors. The DR scheme is implemented on a CNN accelerator based on Xilinx Zynq 7000 SoC, and fault injection (FI) experiments are performed to evaluate the performance of the proposed DR scheme. The results show that it can effectively mitigate the effect of soft errors in the configuration memory with an overhead of about 1.3 times complexity and 1.4 times power consumption relative to those of the unprotected PE array. Compared with the advanced checksum-of-checksum (CoC) scheme, the DR scheme decreases power consumption by up to 30%.

Training deep neural networks (DNNs) on edge devices is appealing for its adaptability and privacy benefits, but it faces challenges due to the limited resources and energy available on edge devices. In this paper, we propose MSCA, a Multigrained Sparsity Convolution Accelerator. MSCA exploits both coarse-grained and fine-grained sparsity during the DNN training phases through two types of well-designed units. Experimental results show that MSCA implemented on FPGA achieves 218.03 GOPS throughput, 39.8 GOPS/W energy efficiency, and 4.0-6.2x speedup over dense accelerators for training VGG-8 and ResNet-10 on the CIFAR-10 and SVHN datasets.

Despite extensive efforts, existing approaches to design accelerators for optimization-based robotic applications have limitations. Some approaches focus on accelerating general matrix operations, but they fail to fully exploit the specific sparse structure commonly found in many robotic algorithms. On the other hand, certain methods require manual design of dedicated accelerators, resulting in inefficiencies and significant non-recurring engineering (NRE) costs.

Batch normalization (BN) plays a critical role in training deep neural networks (DNNs) on energy-limited edge devices since it accelerates the convergence of DNN training. However, the statistical operations and data dependencies within BN introduce challenges to efficient BN hardware design, such as complex computation and repeated data accesses. This paper presents PBN, a progressive batch normalization approach that can decouple the statistical calculation and normalization process within BN to address the above challenges. PBN exhibits considerable accuracy and convergence speed when evaluated using classical DNN models and datasets. Furthermore, a PBN hardware module that supports both forward propagation and backward propagation in DNN training is designed and implemented on Xilinx ZCU102 field-programmable gate array (FPGA). Experimental results indicate that PBN reduces external memory access (EMA) by an average of 80%, while achieving a 2.85× speedup compared with conventional BN.

The approximate multiplier (AM) serves as a computing unit that saves hardware resources and power consumption at the expense of computational accuracy. This paper proposes a data-distribution aware approximate multiplier (DDAM) design for FPGAs. We build a numerical optimization model for automatic design space exploration of DDAM. Furthermore, we propose a weight-based iterative algorithm (WIA) to accelerate the solution of the optimization model. Experimental results demonstrate that WIA significantly reduces DDAM design exploration time to approximately 0.05% of a generic search method. The generated DDAM reduces the average error by about 43% compared to approximate multipliers with uniform data distribution. Furthermore, in an 8 × 8 multiplication scenario, DDAM reduces LUT utilization by 48% compared to the Xilinx’s accurate multiplier IP core. Compared to existing FPGA-based AMs, DDAM achieves the best balance between accuracy and area.

This paper proposes an anti-fault injection attack method for data flow errors of RISC-V processor, which occur when the processor is under fault attacks with clock glitches. To reduce the cost of countermeasure, the method is developed in a hardware and software co-designed manner, based on hardware fault detection and software fault response and recovery. A lightweight clock glitch detection circuit is exploited to detect the glitches and generate the alarm signal. Then the alarm signal triggers the software interrupt handler and the fault recovery interrupt service program executes to restore data. To realize the fault recovery scheme, the minimum micro-architecture modifications of the RISC-V processor and instruction extensions are proposed. The experimental results show that the countermeasure can effectively restore the data and only increases the logic resource usage of the processor by about 3% without affecting the performance.

In the last ten years, the frequent earthquakes have pushed the experts to watch the earth’s movements more closely. Fortunately, recent enhancements in modern High-Performance Computing (HPC) power help researchers understand the internal earthquake mechanisms using the numerical simulation method. Considering the performance and energy requirements, specialized FPGA-based accelerators have become a promising solution for high-performance earthquake simulation. In this work, we propose a resource-aware decomposition framework of earthquake simulation based on an analytic resource model. Then, we demonstrate our efforts in computation design to ensure continuous streaming operation and prevent deadlocks. Compared with the floating-point implementation based on NVIDIA GPU A6000, our design is 1.6 times and 3.4 times better in performance and energy efficiency, respectively.

Recent studies have shown that electromagnetic fault injection (EMFI) attacks can lead to multi-bit faults in DRAM, threatening the security of memory chips. Check codes are widely used to detect the occurrence of faults and to store and transmit information. However, in dealing with the problem of multi-bit faults, classical check codes, like ECC code and parity check, face the risk of failure. Therefore, in this paper, a new error check method based on a lightweight hash function named PHOTON hash is proposed to detect multi-bit faults caused by EMFI in DRAM. Compared with traditional error check methods, the proposed method can effectively detect the occurrence of multibit faults. In order to verify the effectiveness of the proposed method, a simulated fault injection experiment is carried out. The experimental results show that this method can effectively reduce the success rate of fault injection.

The blockchain-based Internet of Things (IoT) has served widely across various industries for authentication, cooperation, and data sharing but faced the severe challenge of storage scalability. The storage burden gets worse for IoT devices with limited resources. The state data is essential for efficient transaction issuance and validation. This article proposes the Verkle accumulator-based stateless transaction validation (VA-STV) scheme for permissionless blockchains to decrease the storage burden of the state data on each node with the acceptable overhead of computation and communication. In the scheme, the current state is summarized as the commitment maintained in the latest block header, and one witness is generated for each token to guarantee its validity. State transitions are realized by updating the commitment and witnesses so that no state is stored on nodes acting as validators and miners. Only the nodes acting as traders should maintain the tokens controlled by themselves and the witnesses locally. The VA-STV is based on the Verkle accumulator (VA), which is a combination of the Verkle tree (VT) and the KZG polynomial commitment scheme. Simulation results show that the VA-STV provides a smaller witness size ($0.6\times $–$0.74\times $) and faster commitment generation ($6\times $–$14\times$) than the existing stateless schemes in the same settings, which indicates the advantages of VA-STV in succinctness and efficiency. Besides, a tradeoff between the communication and computation requirements can be achieved by adjusting the branching factor, which improves the adaptability of the proposed scheme for different IoT scenarios.

The post-training quantization (PTQ) is a common technology to improve the efficiency of embedded neural network accelerators. Existing PTQ schemes for CNN activations usually rely on calibration dataset with good data representation to reduce quantization overflow in inference, which is not always effective due to large variation and uncertainty of the inference input data in practice. This paper proposes an adaptive PTQ method for activations (AQA), which monitors the quantization overflow of activations, adaptively updates the quantization parameters, and re-quantizes the activations on-the-fly when the overflow degree is over a threshold. The key challenges in implementing the AQA method are to reduce the associated side-effects in increasing computational complexity, processing time and hardware resource usage. We propose a series of design optimizations for quantization overflow monitor, quantization parameters update and re-quantization to successfully address the challenges. The proposed AQA method is implemented in a CNN accelerator and evaluated on VGG16, ResNet18 and MobileNetV2 on several datasets. Experiment results show that the adaptation method makes the models’ inference accuracy stable over various quantization overflow degrees, while the static quantization method suffers from significant accuracy degradation. The costs introduced by the adaptation method include 5% power consumption increase and 4% throughput degradation.

FPGAs are drawing increasing attention in resolving molecular dynamics (MD) problems, and have already been applied in problems such as two-body potentials, force fields composed of these potentials, etc. Competitive performance is obtained compared with traditional counterparts such as CPUs and GPUs. However, as far as we know, FPGA solutions for more complex and real-world MD problems, such as multi-body potentials, are seldom to be seen. This work explores the prospects of state-of-the-art FPGAs in accelerating multi-body potential. An FPGA-based accelerator with customized parallel dataflow that features multi-body potential computation, motion update, and internode communication is designed. Major contributions include: (1) parallelization applied at different levels of the accelerator; (2) an optimized dataflow mixing atom-level pipeline and cell-level pipeline to achieve high throughput; (3) a mixed-precision method using different precision at different stages of simulations; and (4) a communication-efficient method for internode communication. Experiments show that, our single-node accelerator is over 2.7× faster than an 8-core CPU design, performing 20.501 ns/day on a 55,296-atom system for theTersoffsimulation. Regarding power efficiency, our accelerator is 28.9× higher than I7-11700 and 4.8× higher than RTX 3090 when running the same test case.

Convolutional neural networks (CNNs) have been widely deployed in computer vision tasks. However, the computation and resource intensive characteristics of CNN bring obstacles to its application on embedded systems. This article proposes an efficient inference accelerator on Field Programmable Gate Array (FPGA) for CNNs with depthwise separable convolutions. To improve the accelerator efficiency, we make four contributions: (1) an efficient convolution engine with multiple strategies for exploiting parallelism and a configurable adder tree are designed to support three types of convolution operations; (2) a dedicated architecture combined with input buffers is designed for the bottleneck network structure to reduce data transmission time; (3) a hardware padding scheme to eliminate invalid padding operations is proposed; and (4) a hardware-assisted pruning method is developed to support online tradeoff between model accuracy and power consumption. Experimental results show that for MobileNetV2 the accelerator achieves 10× and 6× energy efficiency improvement over the CPU and GPU implementation, and 302.3 frames per second and 181.8 GOPS performance that is the best among several existing single-engine accelerators on FPGAs. The proposed hardware-assisted pruning method can effectively reduce 59.7% power consumption at the accuracy loss within 5%.

Factor graph is a graph representing the factorization of a probability distribution function and serves as a perfect abstraction in many autonomous machine computing stacks, such as planning, localization, tracking and control, which are challenging tasks for autonomous systems with real-time and energy constraints.In this paper, we present BLITZCRANK, an accelerator for motion planning algorithms using the abstraction of a factor graph. By formulating motion planning as a factor graph inference, we successfully reduce the scale of the problem and utilize the inherent matrix sparsity. BLITZCRANK is able to realize the user-defined optimal design by finding the optimal order of the factor graph inference. With a domain specific balancing order, BLITZCRANK achieves up to 7.4× speed up and 29.7× energy reduction compared to the software implementation on Intel CPU.

Electromagnetic fault injection (EMFI) attack has posed serious threats to the security of integrated circuits. Memory storing sensitive codes and data has become the first choice of attacking targets. This work performs a thorough characterization of the induced faults and the associated fault model of EMFI attacks on DRAM. Specifically, we firstly carry out a set of experiments to analyse the sensitivity of various types of memory to EMFI. The analysis shows that DRAM is more sensitive to EMFI than EEPROM, Flash, and SRAM in this experiment. Then, we classify the induced faults in DRAM and formulate the fault models. Finally, we find the underlying reasons that explain the observed fault models by circuit-level simulation of DRAM under EMFI. The in-depth understanding of the fault models will guide design of DRAM against EMFI attacks.

The transformer neural networks have achieved remarkable performance in both Natural Language Processing (NLP) and Computer Vision (CV) applications, with encoder-decoder architecture based on attention layers. However, implementing transformers on resource-constrained devices presents challenges due to the super-large network structures and nontrivial dataflows. Field-Programmable Gate Arrays (FPGA) have been a promising platform for Neural Network (NN) acceleration due to their design flexibility and customization. Existing FPGA-based implementations of transformers face efficiency and generality issues. This paper proposes HPTA, a high-performance accelerator for implementing transformers on FPGA. We analyze the structural features of transformer networks and design the accelerator with configurable processing element, optimized data selection and arrangement and efficient memory subsystem, to support various transformers. We evaluate the performance of HPTA with BERT and Swin Transformer, the typical transformer models in NLP and CV. HPTA achieves up to 44× and 29× inference time reductions compared with the CPU implementation, and up to 17× and 10x energy efficiency improvements compared with the GPU implementation, for BERT and Swin Transformer, respectively. Compared to the existing FPGA-based accelerators, HPTA shows performance improvements up to 1.3× and 1.8× in inference time compared to NPE and Vis-TOP, respectively.

This paper presents a portable coprocessor to accelerate digital signal processing (DSP) applications for low power Internet-of-Things (IoT) devices. The DSP coprocessor is based on RISC-V packed-SIMD instructions, and can be tightly integrated with various RISC-V cores as an independent IP by using an extension interface. The DSP coprocessor is verified on a Nexys A7 FPGA. The experimental method includes comparing the clock cycles of hamming codes, fast Fourier transforms (FFT) and digital filters running on the DSP coprocessor integrated with RISC-V cores and on original RISC-V cores. The results demonstrate a significant clock cycle reduction by up to 79.03%, 49.57% and 61.58%, respectively.

The post-training compression based on affine quantization is a common technology to improve the efficiency of embedded neural network accelerators. Current state-of-the-art quantization schemes for CNN activations usually rely on calibration dataset with better data representation to reduce the possibility of quantization overflow in inference, which is not always effective due to the uncertainty of the inference input data in practice. This paper proposes an adaptive quantization method for activations and its hardware-friendly design to directly address the quantization overflow in inference. This method monitors the quantization overflow of activations on-the-fly, adaptively updates the quantization parameters, and re-quantizes the activations when the overflow degree is over a tunable threshold. We evaluate the proposed method on VGG16 and MobileNetV2 and experiment results show that 11% improvement in inference accuracy at severe quantization overflow is achieved with the cost of 3% increase in runtime, and tuning the threshold enables trade-off between inference accuracy and speed.

Accurate and efficient localization of robots under limited on-board resources has fueled specialized localization accelerators. Despite many recent efforts, accelerating robotic localization is still fundamentally challenging. To tackle the challenges, the paper proposes a configurable hardware architecture and a design space optimization method to automatically generate an optimal accelerator design under the design constraints. Data locality, sparsity, and fixed-point arithmetic optimization techniques that are specific to the localization algorithm are exploited to customize the accelerator. In addition, a low-cost runtime configuration mechanism is proposed to enable the accelerator to continuously optimize itself at runtime according to the operating environment to save power while sustaining performance and accuracy. The evaluation on FPGA demonstrates that the proposed accelerator achieves orders of magnitude performance improvement and/or energy savings compared to the software implementation on Intel and Arm CPUs; and substantially outperforms existing FPGA accelerators in terms of performance and energy.

Asian Hardware Oriented Security and Trust Symposium (AsianHOST) is an annual symposium that aims to facilitate the rapid growth of hardware-based security research and development. Hardware security is a fashionable research area in both industry and academia. Its scope is consistently growing to embrace secure design, manufacturing, and deployment of modern and emerging interoperable computing, communication, storage devices, and circuits and systems. The 7th Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022) was held in hybrid mode on December 14–16 in Singapore. Among all the accepted contributions presented at the conference, a subset of top-rated articles was selected and invited for this Special Issue. The invited articles included extended new technical contributions and results and went through a peer-review process consisting of expert reviewers in the related topics. A brief description of the selected articles is as follows.

Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes. Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2 times computational overhead and 1.69 times power consumption overhead compared to the unprotected decoder.

Digital channelizers (DCs) based on the Discrete Fourier Transform (DFT) and polyphase filter banks are widely used in on-board processing (OBP) platforms to extract narrowband sub-channels from a wideband signal efficiently. In high-capacity communication satellite platforms there are always multiple DCs extracting narrowband signals from multiple wideband signals in parallel. Field-programmable gate arrays (FPGAs) are a popular option for the implementation of DCs due to their parallel computing capabilities and good re-configurability, but FPGAs suffer single-event upsets (SEUs) on the space platform. This paper focuses on the efficient protection of parallel DCs with enhanced coding techniques. We first prove that a linear relationship between parallel DCs can be introduced and maintained among the multiple outputs. However, traditional coding schemes cannot be directly applied for the detection of faulty DCs due to the quantization noise introduced by fixed point implementations. To address this issue, we propose an enhanced coding scheme by averaging in the space and time domains to minimize the effect of quantization noise, introducing thresholds and a majority voter to further improve the detection probability. Both theoretical analysis and fault injection experiments prove the effectiveness of the proposed protection scheme. Experimental results show that all the SEUs that cause an SNR lower than 20dB can be detected and recovered, and the resource overheads are about 1.6 times and 1.3 times of that of the unprotected DCs for systems with 8 DCs and 16 DCs, respectively.

No abstract available.

Reed–Solomon erasure codes (RS-ECs) are widely applied in storage and packet communication systems to recover erasures. When implemented on a field-programmable gate array (FPGA) in a space platform, the RS-EC decoder will suffer single event upsets (SEUs) that can cause failures. In this brief, the reliability of an RS-EC decoder implemented on an FPGA to errors on the configuration memory is first studied based on hardware SEU injection experiments. We found that the reliability is lower for larger number of erased symbols, but there are still about 85% SEUs can be tolerated by the decoder itself even for the maximum number of erased symbols within the recovery capability. In addition, around 10%–25% SEUs on critical bits can cause system exceptions. Based on these results, a duplication with comparison (DWC) scheme is proposed for the protection of the RS-EC decoder. In particular, a checksum parity-based approach is proposed to detect the faulty decoder to reduce the computation overhead. Experimental results show that the reliability of the DWC protected RS-EC decoder to SEUs on the configuration memory is almost the same of a traditional triple modular redundancy (TMR) protection, and the resource usage is only about$2.15\times $that of the unprotected decoder.

The post-training compression with quantization is a common technology to improve the efficiency of embedded neural network accelerators. In this paper, a Dynamic Quantization in Inference (DQI) method is proposed to solve the severe quantization overflow problem that may occur in CNN inference process. Based on analysis of quantization errors of activation values in convolutional layers, efficient quantization overflow detection and quantization parameters dynamic update are designed and implemented in CNN accelerator. The evaluation result on VGG16 and MobileNetV2 models demonstrates that DQI can improve the inference accuracy of by up to 11.59% in high overflow scenarios, while the overhead in hardware resources and runtime is acceptable.

Approximate multiplier is a computing unit, which reduces resource and power by sacrificing computational accuracy, and is widely used in fields such as image processing and deep neural networks. In this paper, a low-cost$\mathbf{8}\times \mathbf{8}$unsigned approximate multiplier is proposed by considering FPGA architectural features. A stage-aware most significant bits (MSBs) selection scheme is designed for error recovery to trade off accuracy and resource usage. The proposed multiplier saves up to 19.7% LUT utilization while the accuracy only decreases 4%, compared to the accurate Xilinx multiplier IP.

Factor graph is a graph representing the factorization of a probability distribution function, and has been utilized in many autonomous machine computing tasks, such as localization, tracking, planning and control etc. We are developing an architecture with the goal of using factor graph as a common abstraction for most, if not, all autonomous machine computing tasks. If successful, the architecture would provide a very simple interface of mapping autonomous machine functions to the underlying compute hardware. As a first step of such an attempt, this paper presents our most recent work of developing a factor graph accelerator for LiDAR-Inertial Odometry (LIO), an essential task in many autonomous machines, such as autonomous vehicles and mobile robots. By modeling LIO as a factor graph, the proposed accelerator not only supports multi-sensor fusion such as LiDAR, inertial measurement unit (IMU), GPS, etc., but solves the global optimization problem of robot navigation in batch or incremental modes. Our evaluation demonstrates that the proposed design significantly improves the real-time performance and energy efficiency of autonomous machine navigation systems. The initial success suggests the potential of generalizing the factor graph architecture as a common abstraction for autonomous machine computing, including tracking, planning, and control etc.

In recent studies, a fault analysis method, called persistent fault analysis (PFA), is proposed for cracking block ciphers. Unlike widely used differential fault analysis methods, PFA does not require correct cihpertexts and precise time control of fault injection. The existing PFA methods mainly assume single fault, i.e., the fault injection process induces a single fault in the target cipher devices. However, the existing low-cost fault injection attack (FIA) techniques, such as clock glitch injection and electromagnetic pulse (EMP) injection usually induce multiple faults per injection. Given multiple faults, the existing PFA methods are either not applicable or faced with high computational complexity in practice. In this article, a new PFA method, called MPFA, is proposed for multiple persistent faults, which reduces both the computational complexity and the required ciphertexts. MPFA can be applied to the ciphertexts-only attack scenario, where all fault positions, fault values, and fault quantity are unknown. The experiments show that compared to the existing PFA methods, the MPFA method reduces the required ciphertexts for cracking AES by at least 57.5% and reduces the computational complexity$NF^{16}$times for$NF$faults. The proposed MPFA is also evaluated on the block ciphers LED and PRINCE. Moreover, a real EMP FIA is carried out and the key of AES-128 is successfully cracked by the MPFA method, demonstrating its validity and efficiency.

The Industrial Internet of Things (IIoT) is the essential component of Industry 4.0. Blockchain is a promising technology for secure data sharing and trustable cooperation between IIoT devices. However, the ever-growing transaction records make it difficult for the storage-limited IIoT devices to join the blockchain network. In this article, an adaptive compression scheme is proposed to decrease the storage volume on each node. In the scheme, the block body is compressed by representing the included transactions as their remainders stored in the distributed nodes. The original transaction could be recovered based on the Chinese remainder theorem. In particular, each node adapts its compression ratio according to its storage resource. The nodes storing more data have advantages in transaction recovery, introducing an incentive mechanism for efficient storage utilization. The theoretical analysis and simulation results show that the proposed scheme can achieve a high compression ratio with good service availability. The proposed scheme dramatically lowers the threshold for IIoT devices to join the blockchain network, which is important for the large-scale application of blockchain in Industry 4.0.

Fault injection attack (FIA) has become a serious threat to the confidentiality and fault tolerance of integrated circuits (ICs). Circuit designers need an effective method to evaluate the countermeasures of the IC designs against the FIAs at the design stage. To address the need, this article, based on FPGA emulation, proposes an in-circuit early evaluation framework, in which FIAs are emulated with parameterized fault models. To mimic FIAs, an efficient scan approach is proposed to inject faults at any time at any circuit nodes, while both the time and area overhead of fault injection are reduced. After the circuit design under test (CUT) is submitted to the framework, the scan chains insertion, fault generation, and fault injection are executed automatically, and the evaluation result of the CUT is generated, making the evaluation a transparent process to the designers. Based on the framework, the confidentiality and fault-tolerance evaluations are demonstrated with an information-based evaluation approach. Experiment results on a set of ISCAS89 benchmark circuits show that on average, our approach reduces the area overhead by 41.08% compared with the full scan approach and by over 20.00% compared with existing approaches. The confidentiality evaluation experiments on AES-128 and DES-56 and the fault-tolerance evaluation experiments on two CNN circuits, a RISC-V core, a Cordic core, and the float point arithmetic units show the effectiveness of the proposed framework.

Convolutional neural networks (CNNs) have been widely deployed in computer vision tasks. However, the computation and resource intensive characteristics of CNN bring obstacles to its application on embedded systems. MobileNet, as a representative of compact models, can reduce the amount of parameters and computation. A high-performance inference accelerator on FPGA for MobileNet is proposed in this paper. With respect to the three types of convolution operations, multiple parallel strategies are exploited and the corresponding hardware structures such as input buffer and configurable adder tree are designed. With respect to the bottleneck block, a dedicated architecture is proposed to reduce data transmission time. In addition, a hardware padding scheme to improve the efficiency of padding is proposed. The accelerator implemented on Virtex-7 FPGA reaches 70.8% Top-1 accuracy under 8-bit quantization. The accelerator achieves 302.3 FPS and 181.8 GOPS, which obtains 22.7x, 3.9x and 1.4x speedup compared to the implementations in Snapdragon 821 CPU, i7-6700HQ CPU and GTX 960M GPU, respectively.

We develop and commercialize autonomous machines, such as logistic robots and self-driving cars, around the globe. A critical challenge to our—and any—autonomous machine is accurate and efficient localization under resource constraints, which has fueled specialized localization accelerators recently. Prior acceleration efforts are point solutions in that they each specialize for a specific localization algorithm. In real-world commercial deployments, however, autonomous machines routinely operate under different environments and no single localization algorithm fits all the environments. Simply stacking together point solutions not only leads to cost and power budget overrun, but also results in an overly complicated software stack. This paper demonstrates our new software-hardware co-designed framework for autonomous machine localization, which adapts to different operating scenarios by fusing fundamental algorithmic primitives. Through characterizing the software framework, we identify ideal acceleration candidates that contribute significantly to the end-to-end latency and/or latency variation. We show how to co-design a hardware accelerator to systematically exploit the parallelisms, locality, and common building blocks inherent in the localization framework. We build, deploy, and evaluate an FPGA prototype on our next-generation self-driving cars. To demonstrate the flexibility of our framework, we also instantiate another FPGA prototype targeting drones, which represent mobile autonomous machines. We achieve about $2 \times$ speedup and $4 \times$ energy reduction compared to widely-deployed, optimized implementations on general-purpose platforms.

Targeting at small satellite applications, we propose a lightweight and configurable circuit design for synchronization and demodulation, which are the key processing steps of PDSCH receiver, on FPGA. We design an elaborately pipelined circuit with balanced speed and area, by analysing the operation complexity and sharing resources among the operations. The circuit design is configurable such that the circuit can switch state at run-time to support multiple data rates and modulation schemes. Also, a parametric truncation module is realized to implement the circuit with fixed-point numbers. Experiments prove that the lightweight circuit can perform real-time processing of received data with good demodulation performance.

This paper proposes a digital and lightweight delay- based detector against fault injection attacks (FIAs) which could induce clock glitches. The detector has a simple structure and exploits a reconfigurable delay chain to monitor the clock signal disturbances. The delay chain is designed according to the protected circuit's clock period and timing slack, such that the detector can work in a range of delay values. This property makes the detector tolerate the aging issue. The experiments on iterative DES cipher circuit verify that the detector is effective to detect clock glitches. The overheads of area and power consumption introduced by the detector are 0.058% and 4.5%, respectively.

Despite many recent efforts, accelerating robotic computing is still fundamentally challenging for two reasons. First, robotics software stack is extremely complicated. Manually designing an accelerator while meeting the latency, power, and resource specifications is unscalable. Second, the environment in which an autonomous machine operates constantly changes; a static accelerator design leads to wasteful computation.

Bundle adjustment (BA) is a fundamental optimization technique used in many crucial applications, including 3D scene reconstruction, robotic localization, camera calibration, autonomous driving, street view map generation, and even space exploration etc. Essentially, BA is a joint non-linear optimization problem, and one which can consume a significant amount of time and power, especially for large optimization problems. Previous approaches of optimizing BA performance heavily rely on parallel processing or distributed computing, which trade higher power consumption for higher performance. In this article we propose p-BA, the first hardware-software co-designed BA hardware accelerator that exploits custom hardware to simultaneously achieve higher performance and power efficiency. Specifically, based on our key observation that not all 3D points appear on all images in a BA problem, we designed a Co-Observation Optimization technique to accelerate BA operations with optimized usage of memory and computation resources. In addition, we developed a hardware-friendly differentiation method, which combines the analytic and forward automatic differentiation to calculate derivatives of projection function in the BA problem. We have implemented the proposed design on an embedded FPGA SoC, and experimental results confirm that p-BA outperforms the existing software implementations in terms of performance and power consumption.

Bundle adjustment (BA) is a fundamental optimization technique used in many crucial applications, including 3D scene reconstruction, robotic localization, camera calibration, autonomous driving, space exploration, street view map generation etc. Essentially, BA is a joint non-linear optimization problem, and one which can consume a significant amount of time and power, especially for large optimization problems. Previous approaches of optimizing BA performance heavily rely on parallel processing or distributed computing, which trade higher power consumption for higher performance. In this paper we propose π-BA, the first hardware-software co-designed BA engine on an embedded FPGA-SoC that exploits custom hardware for higher performance and power efficiency. Specifically, based on our key observation that not all points appear on all images in a BA problem, we designed and implemented a Co-Observation Optimization technique to accelerate BA operations with optimized usage of memory and computation resources. Experimental results confirm that π-BA outperforms the existing software implementations in terms of performance and power consumption.

This paper proposes a new partial scan approach in which the problem of selecting flip-flops in partial scan designs is converted to the balanced graph transformation problem based on an integer linear programming formulation. The complexity of the problem is analyzed and a scalable approach is proposed to deal with complicated circuits. Experimental results on a set of benchmark circuits show that on average the proposed approach reduces the area overhead by 25% compared with the full scan approach and by 17.8% compared with the existing balanced structure-based partial scan approach.

In recent years, 3-dimension convolutional neural networks (3D CNNs) have been widely used for video analysis, 3-dimension geometric data and medical image diagnosis. While conventional CNNs are computationally intensive, 3D CNNs push the computational requirements into another level, since each computation depends on multiple image frames. This paper describes a novel hardware architecture for a 3D convolutional neural network, and design strategies to resolve memory usage and bandwidth limitations. The proposed architecture F-C3D is implemented on zc706 at 172MHz, showing 231 times speed up compared with software implementation on 1 GHz ARM CPU, 7.4 times speed up on 3.07 GHz Intel CPU and nearly 10 times lower power consumption than GPU.

FPGA-based hardware emulation platform runs significantly faster than software simulation for verifying complex circuit designs. However, the controllability and observability of circuit internal signals mapped onto FPGAs are restricted due to the limited chip pins. Scan chain-based technique is effective in providing full-chip controllability and observability, at the cost of large area overhead, especially for FPGAs. Therefore, partial scan has been proposed as an alternative way to improve the controllability and observability while reducing the area cost. However, the optimized partial scan solution with the minimum number of scan flip-flops is not always found. This paper formulates the classical balanced structure partial scan procedure in one step as an integer linear programming problem, leading to the optimized partial scan solution. In addition, partially used logic resources in FPGAs are exploited to implement the extra logic required by the scan chain, to further reduce the area cost. Experimental results show that our partial scan approach can reduce the area overhead by 78.6% and 16.6% compared to the full scan and the existing partial scan approach.

Fault injection attacks (FIAs) are becoming a serious threat to the security of integrated circuits (ICs). Circuit designers need a simple and effective method to evaluate the ability of their IC designs against the FIAs at design stage. To address the need, this paper based on FPGA emulation proposes a method, which mimics FIAs on a circuit design implemented on a FPGA by instantiating a uniform architecture which can generate different fault models and span the space of faults and inserting fault injection logic into the design. After the circuit design is submitted to the emulation platform, the fault generation and injection are executed automatically, and a report about the ability of the IC design against the FIAs is generated. The method works at the circuit netlist level, leaves the source codes of the circuit design unmodified, and makes the evaluation a transparent process to the designers. The experiment with various fault models and differential fault analysis on AES-128 encryption circuit shows the effectiveness of the method.

This paper proposes a knowledge-based neural network (KBNN) modeling approach for field-programmable gate array (FPGA) logical architecture design. The KBNN embeds the existing FPGA analytical models (AMs) into an NN. The NN can complement the AMs according to their needs to provide further increased model accuracy, while maintaining the meaningful trends successfully captured in the AMs. The obtained KBNN predicts the routing channel width required by circuit implementations on various FPGA architectures, which can be used by architects to quickly and accurately evaluate various FPGA architectures in early development stages. Experimental results show that the KBNN-based approach achieves an average error of 2%, which shows 75% accuracy enhancement over the existing AMs for routing channel width estimation of a set of benchmark circuits and FPGA architectures. The KBNN model has been applied to three FPGA architecture development scenarios to demonstrate its practical application and effectiveness.

Intellectual property (IP) core reuse is essential for the design process of system-on-chip (SoC). Network-on-chip (NoC) has been used as an independent IP core during SoC design. However, the NoC has not been protected via IP protection and paid attention on its innovations. This paper proposes the first known approach to protect the authorship and the usage legitimacy of NoCs using specially designed routing, square spiral routing. The special routing algorithm exploits routing redundancy inherent in the mesh NoCs and transports packets along the paths, which have very low probability to be taken under commonly used routing algorithms. These unique and diverse paths are exploited in this paper to embed information of the author and identify the legal buyer of NoCs, showing high robustness and credibility. The hardware implementation of an IP-protected mesh NoC shows that the area overhead is small, which is ~0.74%, and the power overhead is ~0.52%, while the functionality and performance of the network is not affected. In this paper, the approach is presented for the mesh NoC, but the idea is equally applicable to other NoC topologies where the unique and diverse paths also inherently exist.

Solar energy prediction is a key to the power management in the electronic embedded system that operates using the harvested solar energy. This paper proposes accuracy improvement approaches for the solar energy prediction based on artificial neural networks, in order to increase the robustness of solar-energy-powered systems. Two complementary neural network models, multilayer perceptron (MLP) network and knowledge-based neural network (KBNN), are exploited to predict the future solar energy, through offline and online training. MLP is constructed under the guidance of the proposed input parameter selection approach and is used when the training data are sufficient. KBNN is employed to take advantage of the existing prediction models and is especially valuable when the training data are insufficient. Built on top of the existing prediction approaches, our work results in a synergy that can overcome the accuracy limitation of the existing prediction approaches. The experimental results show the prediction accuracy improvements by up to 65.4%, compared with the existing approaches. The results also demonstrate the capability of KBNN in providing a reliable model, especially when fewer training data are available.

Hardware Trojans (HTs) can be implanted in security-weak parts of a chip with various means to steal the internal sensitive data or modify original functionality, which may lead to huge economic losses and great harm to society. Therefore, it is very important to perform hardware Trojan detection and diagnosis, find potential safety hazards and apply protection techniques in the whole IC design cycle, in order to enhance the security of chips. In this paper, we elaborate an IC market model, and describe the potential HT threats faced by the parties involved in the model. Then we survey the recent research advances in the countermeasures against HT attacks, which are classified into HT detection, diagnosis and prevention. Finally, the challenges and prospects for HT defense are illuminated.

Emerging System-on-Chip (SoC) applications on FPGAs have boosted the FPGA-based Network-on-Chip (NoC) implementations. Router microarchitecture plays a central role in the performance of an NoC. This paper investigates the router architecture in great detail and designs high throughput architecture based on the fine-grained configurability and customizability provided by FPGAs. Specifically, we 1) divide the logic operations of the router into two pipelining stages and implement a modified backpressure flow control mechanism to support high frequency and pipelined routing operation; 2) explore different buffering schemes to find an architecture which can sustain low queuing delays. The experimental results show that the pipelined architecture achieves operation clock frequency over 400 MHz, which is 3 times higher than that of an open source FPGA-based NoC, CONNECT, leading to about 5 times improvement in the network saturation throughput.

A design approach is proposed to automatically identify and exploit runtime reconfiguration opportunities with optimised resource utilisation by eliminating idle functions. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and runtime solution generation. The synthesised reconfigurable designs are dynamically evaluated and selected under various runtime conditions. Three applications—barrier option pricing, particle filter, and reverse time migration—are used in evaluating the proposed approach. The runtime solutions approximate their theoretical performance by eliminating idle functions and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 43.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.

Through energy harvesting system, new energy sources are made available immediately for many advanced applications based on environmentally embedded systems. However, the harvested power, such as the solar energy, varies significantly under different ambient conditions, which in turn affects the energy conversion efficiency. In this paper, we propose an approach for designing power-adaptive computing systems to maximize the energy utilization under variable solar power supply. Using the geometric programming technique, the proposed approach can generate a customized parallel computing structure effectively. Then, based on the prediction of the solar energy in the future time slots by a multilayer perceptron neural network, a convex model-based adaptation strategy is used to modulate the power behavior of the real-time computing system. The developed power-adaptive computing system is implemented on the hardware and evaluated by a solar harvesting system simulation framework for five applications. The results show that the developed power-adaptive systems can track the variable power supply better. The harvested solar energy utilization efficiency is 2.46 times better than the conventional static designs and the rule-based adaptation approaches. Taken together, the present thorough design approach for self-powered embedded computing systems has a better utilization of ambient energy sources.

Hardware Trojan insertion has raised serious concerns to semiconductor industry and government agencies. Hardware Trojan is usually activated under rare conditions associated with low transition bits in a circuit. The damage includes circuit functional failure or important information leakage. Previous research on hardware Trojan detection is mainly based on side-channel analysis and Trojan activation. Long activation time is a major concern during the detection process. In this paper, we propose a novel approach for efficiently accelerating Trojan activation by increasing the transition activity of rare bits. In particular, the proposed approach increases the bit-level transition activity by controlling signal word-level statistical properties, such as changing the variance and autocorrelation of the signal. In addition, by analyzing the signal propagation statistical properties through various digital signal processing (DSP) operators such as adders and multipliers, the proposed approach can control the statistical properties of internal signals and then enhance the internal bit transition activity from the primary input of the circuit. The proposed approach is evaluated on several circuits. The results show that the transition activity of rare bits can be dramatically increased by up to 166.7 times and Trojan activation time can be reduced by up to 121 times.

In this paper, the work inis analyzed. An error in its theoretical description part is pointed out and illustrated by a simple example. A modification suggestion is proposed to make the theoretical description of the workmore deliberate and thus being used appropriately.

A design approach is proposed to automatically identify and exploit run-time reconfiguration opportunities while optimising resource utilisation. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and run-time solution generation. Three applications, based on barrier option pricing, particle filter, and reverse time migration are used in evaluating the proposed approach. The run-time solutions approximate the theoretical performance by eliminating idle functions, and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 28.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.

A design approach is proposed to automatically identify and exploit run-time reconfiguration opportunities while optimising resource utilisation. We introduce Configuration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and run-time solution generation. Three applications, based on barrier option pricing, particle filter, and reverse time migration are used in evaluating the proposed approach. The run-time solutions approximate the theoretical performance by eliminating idle functions, and are 1.61 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 28.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.

Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation.

We propose a neural network based approach for estimating the total wirelength of a digital circuit, mapped onto an FPGA, before circuit placement and routing. A 3-layer MLP neural network is trained to learn the behavior of a placement tool and then quickly predicts the wirelength of a circuit design with the accuracy similar to one obtained after placement. A priori knowledge about the wirelength of circuit designs can be used to effectively guide the design exploration processes at the early design stages. This breaks the repetitive CAD design flow and reduces the design cycle. In this work, five circuit parameters and two FPGA architecture parameters are considered in the wirelength estimation. The proposed approach is evaluated by comparing the wirelength given by the trained neural networks and the placement tool VPR for the IWLS2005 circuit benchmark. Results show that the neural network's estimation has an average error below 0.6% compared to VPR. The neural network model is also compared to a linear model for the wirelength estimation, showing 7.39 times improvement in the estimation accuracy.

Utility-directed transformations involve changing a design to optimize for given constraints while preserving behavior. These changes are often achieved by techniques such as linear programming or geometric programming. We present a systematic approach composing multiple utility-directed transformations for optimizing and mapping a sequential design onto a customizable parallel computing platform such as a Field-Programmable Gate Array (FPGA). Our aim is to enable automatic design optimization at compile time. Design goals specified by users drive the design transformations. Each utility-directed transformation achieves part of the overall goal, and multiple utility-directed transformations, connected by pattern-directed transformations, are composed to fulfill the overall design requirements. The utility-directed transformations in this work produce performance-optimized designs by exploiting data reuse, MapReduce, and pipelining for the target parallel computing platform. Moreover, it is shown that performing transformations in different orders allows users to trade speed for resources, and design performance for compile time. Several applications are used to evaluate this approach on FPGAs. The system performance of a 64-bit matrix multiplication is shown to improve up to 98 times compared to the original design, in the target hardware platform.

In this work, we explore heterogeneous computing hardware, including CPUs, GPUs and FPGAs, for scientific computing. We study system metrics such as throughput, energy efficiency and temperature, and formulate the problem of workload allocation among computing hardware in mathematical models with regards to the three metrics. The workload allocation approach is evaluated using Linpack on a hardware platform containing one CPU, one GPU and one FPGA. Results show that the heterogeneous computing system with appropriate workload allocation provides high energy efficiency with peak value at 1.1 GFLOPs/W and reduces power consumption by 56.54%; and that workload allocation schemes are significantly different with regards to different system metrics.

This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally intensive applications can be specified. Field-programmable gate arrays are becoming adopted as a computational platform by the high-performance computing community, but there are challenges to extract maximum performance from these devices. Unlike other approaches, our focus is on data memory organization and input–output bandwidth considerations, which are the typical stumbling block of existing hardware compilation schemes. We describe our approaches, which are based on formal optimization techniques, and present some results showing the advantage of exposing the interaction between data memory system design and parallelism extraction to the compiler.

Starting from sequential programs, we present an approach combining data reuse, multi-level MapReduce, and pipelining to automatically find the most power-efficient designs that meet speed and area constraints in the design space on Field-Programmable Gate Arrays (FPGAs). This combined approach enables trade-offs in power, speed and area: we show 63% reduction in power can be achieved with 27% increase in execution time. Compared to the sequential designs, our approach yields designs with up to 158 times reduction in execution time. Moreover, for a given execution time, our combined approach generates designs using up to 1.4 times less power than those produced by the same optimizations applied separately and can also find solutions missed by separating the optimizations.

A promising approach to high-level design is to start initially with an obvious but possibly inefficient design, and apply multiple transformations to meet design goals. Many hardware compilation tools support a fixed recipe of applying design transformations, but designers have few options to adapt the recipe without re-writing the tools themselves. In addition, complex transformations based on linear programming and geometric programming are often not included. This paper proposes anew approach that enables designers to customize the composition and parameterization of different types of design transformations in a unified framework, using a high-level language to control a transformation engine to automate the application of design transformations. Our approach is implemented by a tool based on the Python language and the ROSE compiler framework, which supports both syntax-directed transformations such as loop coalescing, and goal-directed transformations such as geometric programming. We illustrate how customizing the composition and parameterization of design transformations can lead to designs with different trade-offs in performance, resource usage, and energy efficiency. We evaluate our approach on benchmarks including matrix multiplication, Monte Carlo simulation of Asian options, edge detection, FIR filtering, and motion estimation.

This paper describes a scripting engine based on the Python language and the ROSE compiler framework. Our scripting engine supports hardware design involving both syntax-directed transformations such as loop coalescing, and goal-directed transformations such as geometric programming. We show how customizing the composition and parametrization of design transformations can lead to designs with different trade-offs in performance and resource usage.

We propose a new approach, based on a set of convex models, to accelerate an application using a computing cluster which contains field-programmable gate arrays (FPGAs). The computationally-intensive tasks of the application are mapped onto multiple acceleration nodes, and the datapaths on the nodes are customized around the tasks during compilation. We propose models for computation and communication on the FPGA-based cluster, and formulate the design problem as a convex non-linear optimization problem allowing design exploration. We evaluate our approach on a cluster with 16 nodes for Monte Carlo simulation, resulting in a design 690 times faster than a software implementation.

We present a methodology for optimising designs written in high-level descriptions, combining mathematical model-based transformations with syntax-driven pattern-matching transformations, showing how the two kinds of transformation can benefit each other. We evaluate thismethodology by implementing an instance, combining a model-based transformation for data reuse with pattern-based transformations to improve its output. Results for three benchmarks show the implemented framework can improve system performance by up to 57 times.

A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-calledgeometricprogrammingproblems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times.

A geometric programming framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) exploitation and loop-level parallelization, in the context of FPGA-targeted hardware compilation. We expose the dependence between data reuse and data-level parallelization and explore both problems under the on-chip memory constraint for performance-optimal designs within a single optimization step. Results from applying this framework to several real benchmarks demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework, and performance improvements up to 4.7 times have been achieved compared with the method that first explores data reuse and then performs parallelization.

FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one of the main obstacles to overcome when trying to accelerate an application on an FPGA is the bottleneck in off-chip communication, typically to large memories. Often it is known at compile-time that the same data item is accessed many times, and as a result can be loaded once from large off-chip RAM onto scarce on-chip RAM, alleviating this bottleneck. This paper addresses how to automatically derive an address mapping that reduces the size of the required on-chip memory for a given memory access pattern. Experimental results demonstrate that, in practice, our approach reduces on-chip storage requirements to the minimum, corresponding to a reduction in on-chip memory size of up to 40times (average 10times) for some benchmarks compared to a naive approach. At the same time, no clock period penalty or increase in control logic area compared to this approach is observed for these benchmarks.

Compilation of high level descriptions to field programmable gate array hardware forms a promising option for the efficient mapping of computationally intensive applications under tight development time constraints. In this paper data reuse exploration on top of an existing hardware compilation environment is discussed. The full search motion estimation algorithm for video processing is used as a test vehicle. The systematic approach adopted for the exploration of the data reuse space is described. Experimental results prove that the exploitation of data reuse may lead to more than 80% reduction of the execution time and up to 95% reduction of the off-chip memory accesses.