There has been great effort in programming languages make FPGAs easier to use. On the other hand, there is little progress in the execution environment, especially operating systems, for the support of FPGA. The operating system basically treats the FPGA in the same way as regular non-reconfigurable hardware devices. Therefore, the programmability of FPGA is not fully exploited. This paper proposes an operating system framework for transparent execution of a program on a CPU and FPGA. It enables the execution of a program to be off-loaded to FPGA on demand by making FPGAs programmable computing resources by making programs that utilize FPGAs to be executed transparently on a CPU. The paper shows the experiment results that the proposed framework enables the reduction of the total execution time of a program by parallel execution of the program and the initialization of FPGA.

Memory storage technologies, such as next generation non-volatile (NV) memory and battery backed NV-DIMM, are emerging. While they provide much higher performance than the current block storage devices, such as SSDs and HDDs, their capacities are limited. Such limitation makes it difficult to adapt memory storage for mass storage; thus, its uses have been limited. This paper proposes a method that combines block storage with memory storage and makes use of memory storage as cache of block storage. The proposed method effectively utilizes the high performance of memory storage and also provides the large capacity of block storage. Therefore, memory storage can be transparently used as a part of mass storage while its low overhead access can accelerate storage performance. The proposed method was implemented as a device driver of the Linux kernel. Its performance evaluation shows that it outperforms a bare SSD drive and a drive that combines memory storage and a SSD by the existing method.

The mobile devices such as smartphones and tablets are increasing processor speed and they are desired more energy. We focus on the emerging non volatile memory (NVM), which has gained attention in recent years. A non volatile memory is new memory technology such as SST-MRAM, PCM and ReRAM. Any devices also can be accessed in byte units, high speed nanoseconds access latency and higher write endurance than the flash memory. Thus, it is possible to replace the DRAM of the main memory by the NVM, it is possible to achieve reducing the power consumption. Although potentially possible of large capacity, NVM product of capacity greater than DRAM is currently not appeared now. We should provide a large memory space without performance degradation by in combination with NVM and other memory devices. In this paper, we propose a method to use the DRAM as swap space. The proposed method provides an experimental design of the non volatile main memory system. It enables both of high-performance and energy efficiency.

Non-volatile memory (NVM), such as PCM, STTMRAM, and ReRAM, makes it possible to integrate secondary storage into main memory. This integration reduces I/O access times to typically slow block devices; however, it is unrealistic to construct a large capacity main memory with a single NVM at this time, because NVM have disadvantages regarding write access. Combining NVM and other memory devices is necessary to hide such disadvantages. In particular, we should place writehot data on DRAM and write-cold data on NVM. For data placement, programming language runtime supports are useful, since they have more detailed information about write access than the operating system. A previous study proposed a method to manage NVM/DRAM hybrid memory with programming language runtime supports, determining data placement based on the number of write accesses to each object (i.e., the individual counting method); however, this approach has two problems, namely memory efficiency and determination of threshold values for data placements. The Most Recent Write (MRW) queue method is an alternative method to distinguish between write-hot data and write-cold data. MRW queue manages the frequency of write accesses to objects. In this study, we discuss the problems of the individual counting method and show solutions using the MRW queue approach. Results of our experimentation show that the MRW queue method improves memory efficiency and reduces overhead of the individual counting method.

The advance of the technologies surrounding non-volatile memory (NVM) storage brings the significant improvement of its performance. While such hardware technologies progress, the software technologies for storage stagnate. The current I/O architecture of the operating system (OS) kernel to interact with storage devices was designed a long time ago when HDDs were very slow, and is beginning to cause a mismatch with high performance NVM storage. Such a mismatch is further exaggerated in virtualized environments since the software layers duplicated in a guest and its host kernels create a long I/O request processing path. Because virtualized environments play an major role to enable cloud computing and also because big data processing requires high performance storage access, the I/O architecture for virtualized environments has to be reorganized in a way that it can fully utilize the high performance of NVM storage. This paper proposes a novel storage virtualization method that virtualizes storage as memory, so that virtualized storage provides memory interface. We call such storage virtualized as memory virtual main memory storage (VMMS). VMMS removes the duplication of I/O software layers, and significantly shortens the I/O request processing path. VMMS was implemented in Linux that employs KVM (Kernel-based Virtual Machine) as virtualization software. The evaluation results of VMMS performed on a RAM disk drive and a SSD show that VMMS enables the significant reduction of I/O costs and scales much better than the current I/O architecture.

Reducing power consumption is a serious issue for today's computer systems. The measure to that issue, nonvolatile memory (NVM) and heterogeneous multicore architecture (HMA) draw attention. Non-volatile memory is the device that can maintain data without continuous power supply. This nonvolatile memory enable to reduce power consumption of main memory and zero-overhead hibernation. Heterogeneous multi-core architectures combine different cores. The cores are different each other in terms of instruction set architecture, circuit size and so on. Combination of various characteristics has significant possibility to achieve energy-efficient computer system. For the above reasons, combination of NVM and HMA enable to reduce power consumption of today's computer systems. Assuming using non volatile main memory, Operating System (OS) must be strict about memory management. Because, running time of OS go longer and risk of memory leaks get higher. In addition, code quality of OS must be high. To keep code quality, strong typing is useful. However C, which is mainstream of OS implementation, do not have mechanism avoid memory leak and strong typing mechanism. To solve this issue, there are some researches of implementing OS in Java have many case. However, previous works have certain performance problem. To solve this, we propose a new operating system architecture. This architecture aims that native machine code run as user programs while OS kernel is implemented in java. In this paper, we describe proposed architecture, explain a preliminary implementation of it, and show experiment by that implementation.

Smartphones become popular. They have various sensors and connection modules. They employ a mobile operating system for the control of sensors and modules. In this situation, a large amount of data comes to the operating system from sensors and modules. While such data is important for effective operations of smartphones, it is not well known that how it affects the operating system performance. In this paper, we prepare an experiment environment that mimics a smartphone. We selected the Android as an operating system and the Pandaboard-ES as a target board. The Pandaboard-ES equips a Bluetooth module. We select Wii Remote to operate the Android via Bluetooth. We implement programs to use Wii Remote as the input device of the Android, and improve this program. We make change a profiling software for the Linux and are enable to use it on the Android.

Active research and development efforts on byte addressable non-volatile (NV) memory technologies, such as STT-RAM, PCM, and ReRAM, have been conducted in recent years. Because they are byte addressable, they can be used as main memory by directly connecting them to CPUs. Because they are non-volatile, they can also be used as storage device. While there were the active researches on their use for either main memory or secondary storage, these researches were conducted independently. This paper presents the memory management methods that enable the integration of main memory and file systems, thus, both main memory and storage are realized on the same byte addressable NV memory. The presented methods construct a file system on NV memory, and memory blocks assigned to files are exported for the use of main memory. We implemented the proposed methods in the Linux kernel, and performed their evaluation. The evaluation results show that the file-based methods can perform comparably to the existing DRAM memory allocator and can maintain the consistency of a file system.

Byte addressable non-volatile (NV) memory, such as STT-RAM, MRAM, and PCM, is the next generation memory that can be used as both main memory and secondary storage. While it can persistently store data without power supply, its access speed is comparable to DRAM. While there have been the active researches on its use for either main memory or secondary storage, these researches were conducted independently. This paper presents the integration methods of the main memory and file system management for NV memory, so that it can be used as both main memory and storage. The presented methods use a file system as their basis for the NV memory management; thus, the internal data structures of a file system can have impacts upon the performance of the integration methods. We implemented the proposed methods in the Linux kernel, and performed the evaluation on a system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory.

This paper proposes an extensible RTOS (real-time operating system) architecture for embedded heterogeneous muti-core processors, which consist of processors with different processing power and functionalities. The architecture splits the RTOS kernel into the two components, the proxy kernel (PK) and user-level kernel (UK). The PK runs on a less powerful core, and delegate its functions to the UK that runs on a powerful core as a user process. The UK takes responsibility for the dynamic resource management functions, thus, the PK can focus on the basic but important RTOS functionalities, such as timing management, synchronization, and dispatching the highest priority process. The experiment results running micro benchmark programs show that the proposed architecture can achieve the faster creation and invocation of processes and that a communication cost between the PK and the UK is negligible.

We have been developing Hybrid OpenCL, which enables the utilization of OpenCL devices by connecting them over the network. Hybrid OpenCL opens a gate to scale up OpenCL environments. By using Hybrid OpenCL, applications written in OpenCL can be easily ported to high performance cluster computers, thus, Hybrid OpenCL can provide more various distributed and parallel computing platforms. Hybrid OpenCL consists of two elements, a runtime system that provides the abstraction of OpenCL implementations and a bridge program that connects multiple OpenCL runtime systems over the network. This paper describes the design and implementation Hybrid OpenCL. Its performance for distributed processing is evaluated by using multiple nodes. The experimentation results show that the overhead introduced by Hybrid OpenCL is minimum and comparable with the combination of MPI and OpenCL.

There are several advantages to use virtual machine monitors (VMMs) for better security, reliability, and/or availability of systems. As embedded systems become more complex and open systems, there are more reasons to employ VMMs on embedded systems. Although there are more temptations to use VMMs, there are only a small number of VMMs available for embedded systems, and more of them are commercial proprietary software. Therefore, we decided to develop our own VMM on the ARM processor. We call it SIVARM: a simple VMM for the ARM architecture, because it is based on a simple trap and emulation model to virtualize the ARM processor. Since the VMM executes in privileged mode and its guest OS executes in non-privileged mode, the VMM can catch the execution of sensitive instructions as exceptions and emulate them appropriately. The guest OS can execute in non-privileged mode thanks to the virtual banked registers and the virtual processor mode provided by the VMM. The VMM was implemented for the ARM 1136JF-S processor, and can successfully boot Linux on it.

The emergence of functional embedded systems such as cell-phones and digital appliances brought up a new issue, building a system supporting both real-time and rich services. One of the solutions is leveraging a hypervisor to integrate an RTOS and a commodity OS into a single device. However, this approach induces the limitation of application deployment; all the high priority tasks should reside in the RTOS. In this paper, we propose a task grain scheduling for a real-time hypervisor, which enables a flexible application deployment between an RTOS and a commodity OS. We constructed a prototype system with an existing hypervisor, an RTOS, and a commodity OS. We measured some basic overheads, and fixed some tasks which were missing their deadlines using the task grain scheduling to meet their deadlines. The overheads were small and the task grain scheduling achieved a flexible real-time scheduling for the hypervisor based system.

Demands are increasing for consolidating multiple OSes on a single multi-core CPU rather than using multiple sets of an OS and a CPU. A VMM enables multiple guest OSes to run concurrently on one CPU while providing separate security domains. We have developed Gandalf a lightweight VMM targeting embedded systems with multi-core CPUs. This paper focuses on the shadow paging mechanism of Gandalf which enables physical memory isolation among guest OSes by separating guest page tables from CPUs, because shadow paging significantly affects VMM overheads and is a key to make a VMM lightweight. We designed and implemented two models of shadow paging, single shadow model and multiple shadow model. The measurement results show that they are realized lightweight.

In ubiquitous computing environments, our daily lives will be made convenient by embedded intelligent devices. Those devices, such as car navigation systems, personal digital assistances, and cellular phones, provide various kinds of the complex services. Those devices are networked with each other and provide complicated services, through the Internet. While they provide useful services, there is an increasing possibility of security attacks, which include the unexpected execution of unsecure codes. Current information appliances have not yet fully embodied a resource protection mechanism that prevents misbehaved applications from consuming the whole CPU capacity of system resources. In this paper, we propose accounting system, and describe its design and implementation. The system is a resource monitoring and restriction system that has the purpose of improving the system's reliability and security. We developed the system on Linux. Our system is a very generic to offer various services, such as security improvement, overload control, and class-based accounting, that require CPU resource control

Embedded operating system (OS) kernels provide basic execution primitives that can be used commonly by many appliances. The recent emergence of digital appliances requires more advanced features, such as networking and GUI. Those features dramatically complicate the appliances' software systems and increase their code sizes. In order to develop such large and complex software systems, we propose a system architecture that co-locates multiple embedded operating systems on a microkernel. The proposed architecture employs a microkernel to provide protected execution environments for the existing embedded kernels. In each protected execution environment, a kernel and its applications run just as they run directly on hardware since they share the same protection domain. Our approach can achieve the maximum reusability of the existing software resources including embedded OS kernels and their applications; thus, it protects the existing software resources. We have developed the system that consists of TL4 microkernel and a /spl mu/ITRON embedded kernel, and shows the feasibility of our approach through evaluations.

Embedded computers pervade our lives. There are increasing opportunities for them to adopt embedded operating systems as they are required to have high functionality and complexity. Unfortunately, the reliability of such embedded systems is insufficient to support our lives in 24/7. Therefore, we propose the fine-grain proactive recovery (FPR) of operating system components. FPR enables an operating system to periodically restart its modules and thus to keep their states clean.