The fast growing complexity of today's real time embedded systems necessitates new design methods and tools to face the problems of design, analysis, integration and validation of complex systems. the author presents a system level design method for embedded real-time systems combining the informal strengths of UML with the formal strengths of SDL. The flow is demonstrated by the design example of a telecommunications application from the wireless or access domain, showing the applicability of the flow to control and data-dominated types of systems. Finally, the author shows how the application results and other enduser needs and requirements influenced the current UML 2.0 proposal with support for real-time and embedded systems.

We address the issue of standards development for the system-level design space. System-level design IP re-use standards are key to the future of the VSIA. However, the concept of system-level standards has its share of sceptics: what role can standards play in this developing market segment? In response we present an overview of three standards in the system-level VC integration space, and describe two distinct industrial case studies to support their practicality.

The fast growing complexity of today's real time embedded systems necessitates new design methods and tools to face the problems of integration and validation of complex systems. We have combined a number of different hardware and software methods into one system level design method. The proposed flow is based on UML concepts, executable specifications and platform based design.

In embedded network applications, typically a very large part of the area cost is due to memory units. Also the power for such applications is heavily dominated by the storage and transfers. Given its importance, we have developed a systematic memory management methodology in which the storage related issues are optimized as a first step. In this paper, we present our methodology for embedded network applications. It includes both a dynamic memory management stage, where the data types and virtual memory managers are defined, and a physical memory management stage, where the custom memory architecture is defined. As demonstrated on an industrial example, the application of the methodology results in a heavily power and/or area optimized custom memory architecture for a given application.

In this paper, we present the problem of storage bandwidth optimization (SBO) in VLSI system realizations. Our goal is to minimize the required memory bandwidth within the given cycle budget by adding ordering constraints to the flow graph. This allows the subsequent memory allocation and assignment tasks to come up with a cheaper memory architecture with less memories and memory ports. The importance and the effect of SBO is shown on realistic examples both in the video and asynchronous transfer-mode (ATM) domains. We show that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous memory accesses. Our problem formulation leads to the optimization of a conflict (hyper) graph. For the target domain of ATM, only flat graphs without loops have to be treated. For this subproblem, a prototype tool has been implemented to demonstrate the feasibility of automating this important system design step.

Matisse is a design flow intended for developing embedded systems characterize dby tight inter action b etwe encontrol and data-flow behavior, intensive data storage and tr ansfer, dynamic creation of data, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a cocurr ent obje ct-oriented language, to an optimize d embedded single-chip HW/SW implementation. Matisse supp orts stepwise system-level exploration and refinement, memory architecture exploration, and gradualincorporation of timing constr aints b efore going to tr aditional tools for HW synthesis, SW compilation, and HW/SW interprocessor communication synthesis. Application of Matisse on telecom protocol processing systems shows significant improvements in area usage and power c onsumption.

This paper presents a new formal method for the efficient verification of concurrent systems that are modeled using a safe Petri net representation. Our method generalizes upon partial-order methods to explore concurrently enabled conflicting paths simultaneously. We show that our method can achieve an exponential reduction in algorithmic complexity without resorting to an implicit enumeration approach.

We describe a system design methodology well-suited for telecom network applications. This methodology is being developed into a compiler called Matisse. The entry point for this methodology is a system specification model that is first compiled into an abstract machine. The abstract machine is implementation-independent, which permits the exploration of different embedded hardware/software realizations. The proposed methodology and tools bridge the gap between system specification and synthesis tools commercially available. This yields several advantages over the design methodology currently used in industry.

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Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other.This paper is concerned with the problem of synthesizing such hierarchically defined systems.When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification.Specifically, we consider how one can find the set of implementations that can be "correctly substituted" for a component in the system while preserving the behavior of the total system.The notion of correct substitution is formally defined for a hierarchical network of possibly non-deterministic modules and a new solution framework based on trace theory is presented to compute and represent this complete set of correct substitutions.We show that the complete set can be captured by a single trace structure using the notion of a "maximal trace structure".We indicate how asynchronous synthesis methods may be applied to explore the solution space e.g. to generate a delay-insensitive implementation.

Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently available hardware synthesis environments typically do not support dynamic data structure concepts and their associated memory synthesis problems. In this paper we address the background memory management task in a hardware design trajectory, which includes allocation of a distributed memory architecture, assignment and mapping of abstract data structures to memories, and synthesis of dynamic management behavior. With this approach to explore for the optimal memory architecture, the design entry point is lifted to a higher level than currently used for behavioral synthesis, as the specification can be a high-level program using data abstraction. The power of our approach will be substantiated on an industrial high-performance telecommunication ASIC design.

Abstract Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially communicate in complex and intricate ways. When designing communicating asynchronous modules, several difficult problems arise. First, even if each individual module can be synthesized correctly, according to the environmental assumptions specified for that module, the composition of the communicating modules may not work properly. Thus, one needs to have a way to model how the modules interact with each other, and to verify that their cooperation is consistent. In addition, means should be provided for communication and synchronization at a level higher than signal transitions, and for exploiting the communicating nature of these modules in optimization. This paper proposes a communicating Petri net model for describing communicating asynchronous modules. Each module is modeled by means of a labeled Petri net that extends the widely used Signal Transition Graph model by providing an abstract synchronization mechanism based on rendez-vous semantics. This enables the designer to specify high-level communication as well as low-level details such as signal transitions. Abstract synchronization events are expanded automatically to low-level handshake signals. We have developed a new algebra for communicating Petri nets that is applicable to general Petri nets, involves no unfolding, and defines hiding as generalized net contraction. We have developed methods based on this formal algebra that can be used to manipulate communicating interface modules, to verify their consistency, and to use them as a basis for optimizations. 1.

An important practical approach to automatic verification of finite state concurrent systems is temporal logic model checking.However, a major barrier towards wider application of such methods is the state explosion problem that often occurs during the composition of complex communicating systems.In addition to being large, many systems have very deep state spaces as well.In this paper, we propose an abstraction method based on time abstraction which can significantly reduce both the size as well as the depth of the state space that must be explored during model checking.It is especially suited for applications involving systems that are loosely coupled in the sense that communication activity is relatively sparse, such as applications involving DSPs, which have large intervals of autonomous processing, with communication activity in between.All properties expressible with the temporal logic CTL or CTL -X are strongly preserved under the proposed abstraction.In particular, we give a method that can replace a chain of states by a single state with a time label.The abstracted model is represented by means of a timed label transition system model.We give a composition algorithm for composing the individually time abstracted models to form a global model that can be converted back to a conventional, but potentially much reduced,state space suitable for model checking.Furthermore, a similar approach can be followed in dealing with wait states in which a system is idling while waiting for an escape signal.For many cases, our approach is successful in alleviating the state explosion problem that often arises in composition of communicating systems.