Dai Watanabe

dblp:61/5338 · DBLP profile ↗
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12ranked-venue papers
7as first author
1since 2021 · last 2024
0000-0002-1758-0887ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 10 · 6 first-author · 1 since 2021Theory of computation · 2 · 2 first-author · 1 since 2021Software engineering, systems software and programming languages · 1
YearPublicationVenuePosition
2024 Practical Key Management for Searchable Symmetric Encryption Using Fuzzy Extractor
abstract
With the spread of cloud computing, information leakage from the cloud is recognized as one of the significant issues. Searchable symmetric encryption has been expected to be a core technology that fundamentally solves this problem. On the other hand, the technology has the security advantage of protecting data in the cloud, instead of the users being responsible for strictly controlling their secret keys. Computer environments and IT literacy vary from user to user, therefore it is important to note that users may be exposed to the risk of attackers gaining unauthorized access to their secret keys. This background underlines the importance of user's key management. In this paper, we propose a method that secures and simplifies this process by encrypting and storing the secret key of SSE using a fuzzy extractor. This method not only enhances the security of SSE but also offers significant benefits for end users, such as the ability to operate in multiple computer environments, thereby providing a more flexible and user-friendly experience. We implemented the proposed method on a laptop computer running Windows 10 and a smartphone running Android OS, which are the users' typical execution environments. As a result, we confirmed that the proposal performs practical application.
Dai Watanabe, Masayuki Yoshino
ISITA1
2014 Chaskey: An Efficient MAC Algorithm for 32-bit Microcontrollers
Nicky Mouha, Bart Mennink, Anthony Van Herrewege, Dai Watanabe, Bart Preneel, Ingrid Verbauwhede
Selected Areas in Cryptography4
2013 Key Update Mechanism for Network Storage of Encrypted Data
abstract
Cryptography is now popularized and is widely used anywhere for many aims such as data confidentiality and integrity. The key of cryptography has a lifetime, thus a key update issue is well-known to be one of hard problems in practice. According to the National Institute of Standards and Technology SP 800-57, the lifetime of the cryptographic key and the lifetime of encrypted data are strictly limited. In other words, the encrypted data is required to be periodically re-encrypted. In this paper, we point out that this key update issue is now crucial in network storage and propose a key update mechanism efficiently reducing the communication and computation cost of re-encryption.
Dai Watanabe, Masayuki Yoshino
CloudCom (1)1
2011 Finding Collisions for Reduced Luffa-256 v2 (Poster)
Bart Preneel, Hirotaka Yoshida, Dai Watanabe
ACISP3
2010 Higher Order Differential Attack on Step-Reduced Variants of Luffa v1
Dai Watanabe, Yasuo Hatano, Tsuyoshi Yamada, Toshinobu Kaneko
FSE1
2010 Update on Enocoro stream cipher
abstract
Enocoro is a family of stream ciphers proposed by Watanabe et al. in 2007. It consists of two algorithms called Enocoro-80 and Enocoro-128v1.1, whose key lengths are 80 bits and 128 bits respectively. In this paper, we show that Enocoro-128v1.1 is vulnerable against the related-key attack in which we assume a stronger attacker than one in the related-key differential attack. The attack is applicable with 2112out of 2128keys and the calculation complexity of the attack is about 265. Our attack is mainly of theoretical interest and do not present a threat to practical applications using Enocoro-128v1.1. In addition, we propose to update Enocoro-128v1.1 to Enocoro-128v2 where a patch has been applied to prevent the attack.
Dai Watanabe, Toru Owada, Kazuto Okamoto, Yasutaka Igarashi, Toshinobu Kaneko
ISITA1
2008 Enocoro-80: A Hardware Oriented Stream Cipher
abstract
Panama is a pseudo-random number generator proposed by Daemen and Clapp in 1998. It is designed to achieve high performance in software implementations, and the throughput is twice as fast as that of the AES block cipher. On the other hand, the size optimized implementation in hardware circuit is much larger than that of the AES. We are attempted to design a new hardware oriented PRNG which has a similar structure to Panama. In this paper, a family of PRNGs Enocoro is presented and especially a specific algorithm Enocoro-80 for 80-bit key is given. Enocoro-80 can be implemented with 2.7 Kgates in ASIC. The implementation results are comparable to other ciphers selected as the eSTREAM Profile 2 candidates (hardware oriented ciphers). As a result, we confirm that the design of Panama is suitable to not only a software oriented cipher, but also a hardware oriented cipher.
Dai Watanabe, Kota Ideguchi, Jun Kitahara, Kenichiro Muto, Hiroki Furuichi, Toshinobu Kaneko
ARES1
2007 MAME: A Compression Function with Reduced Hardware Requirements
Hirotaka Yoshida, Dai Watanabe, Katsuyuki Okeya, Jun Kitahara, Hongjun Wu 0001, Özgül Küçük, Bart Preneel
CHES2
2004 A MAC Forgery Attack on SOBER-128
Dai Watanabe, Soichi Furuya
FSE1
2002 A New Keystream Generator MUGI
Dai Watanabe, Soichi Furuya, Hirotaka Yoshida, Kazuo Takaragi, Bart Preneel
FSE1
2001 The New ATC Systems with an Autonomous Speed Control with On-Board Equipment
abstract
The paper introduces a new digital ATC (automatic train control device) system developed by East Japan Railway Company (JR East). In the current ATC, the central ATC logic device calculates permissive speed of each blocking section and controls speed of all trains. On the other hand, in the new digital ATC, the central logic device calculates each position to which a train can move safely, and sends the information on positions to all trains. On each train, the on-board equipment calculates an appropriate braking pattern with the information, and controls velocity of the train. That is, in the new system, the device on each train autonomously calculates permissive speed of each train. These special features realize ideal speed control of each train, making full use of its performance for acceleration and deceleration, which in turns allows high-density train operations.
Masayuki Matsumoto, Akiyoshi Hosokawa, Satoru Kitamura, Dai Watanabe, Atsushi Kawabata
ISADS4
2001 Dependable Automatic Train Control System Using Digital Track Signals
abstract
An architecture for an ATC (automatic train control) system using digital track circuit signals is presented. Its key ideas are the following. (1) Digital track signals expand flexibility of the ATC system design without compromising safety. In comparison with the present analog type ATC typically in use, the probability of the new system being down is expected to drop below one third, and the space occupied by equipment for the new system is halved. (2) Jointless track circuits realize an overlay track circuit compatible with current track circuits. (3) The unity control zone, consisting of a few stations, can function whether a neighboring zone exists or not. (4) The multifunction ATC device on board can process present and new ATC signals simultaneously. (5) Items (2), (3) and (4) allow step-by-step system construction.
Masayuki Matsumoto, Tadao Tsurumaki, Tatsuya Shigeta, Korefumi Tashiro, Dai Watanabe
PRDC5