Firat Kiyak

dblp:61/61 · DBLP profile ↗
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5ranked-venue papers
2as first author
2since 2021 · last 2024
—ORCID · none

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Computer networks · 2 · 1 first-authorTheory of computation · 2 · 1 first-author · 2 since 2021Security and privacy · 1
YearPublicationVenuePosition
2024 Energy complexity of regular languages
Firat Kiyak, A. C. Cem Say
Theor. Comput. Sci.1
2022 Energy Complexity of Regular Language Recognition
Öykü Yilmaz, Firat Kiyak, Meriç Üngör, A. C. Cem Say
CIAA2
2011 Improving robustness of DNS to software vulnerabilities
abstract
The ability to forward packets on the Internet is highly intertwined with the availability and robustness of the Domain Name System (DNS) infrastructure. Unfortunately, the DNS suffers from a wide variety of problems arising from implementation errors, including vulnerabilities, bogus queries, and proneness to attack. In this work, we present a preliminary design and early prototype implementation of a system that leverages diversified replication to increase tolerance of DNS to implementation errors. Our design leverages software diversity by running multiple redundant copies of software in parallel, and leverages data diversity by sending redundant requests to multiple servers. Using traces of DNS queries, we demonstrate our design can keep up with the loads of a large university's DNS traffic, while improving resilience of DNS.
Ahmed Khurshid, Firat Kiyak, Matthew Caesar 0001
ACSAC2
2011 Better by a HAIR: hardware-amenable Internet routing
Brent Mochizuki, Firat Kiyak, Eric Keller, Matthew Caesar 0001
Comput. Networks2
2009 Better by a HAIR: Hardware-Amenable Internet Routing
abstract
Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significant scaling challenges in the presence of ever-increasing routing table growth and churn. Recent advances in programmable hardware and high-level hardware description languages provide the opportunity to implement BGP directly at the hardware layer. Hardware-based implementation allows designs to take advantage of the parallelization and customizability of the underlying hardware to improve performance. As a first step in this direction, we design and implement a hardware-based BGP architecture. To understand the challenges in doing this, we propose an architecture and logical design for the core components of BGP running as a logical circuit in an FPGA. We then enumerate sources of complexity and performance bottlenecks, and derive modifications to BGP that reduce complexity of hardware offloading. Our results based on update traces from core Internet routers indicate an order of magnitude improvement in processing time and throughput.
Firat Kiyak, Brent Mochizuki, Eric Keller, Matthew Caesar 0001
ICNP1