Demo Data from VLDB 2026 / reviewers in the wild / expert
Mike Jorda
dblp:61/6234
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Computer networks
1 paper |
Internet architecture and protocols · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols › local area network
switched ethernet |
0.0 | 1 | 2004 | Verifying a gigabit ethernet switch using SMV · DAC 2004 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2004 | Verifying a gigabit ethernet switch using SMV · DAC 2004 |
Electronic design automation
model checking |
0.0 | 1 | 2004 | Verifying a gigabit ethernet switch using SMV · DAC 2004 |
Methods — techniques the papers use, named apart from their topics
induction · 0.1SMV · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Verifying a gigabit ethernet switch using SMVabstractWe use model checking techniques to verify a switching block in a new Gigabit Ethernet switch - BCM5690. Due to its dynamic nature, this block has been traditionally difficult to verify. Formal techniques are far more efficient than simulation for this particular design. Among 26 design errors discovered, 22 are found using formal methods. We then improve our model checking capability to analyze switch latency. We also use induction to avoid state explosion in the model checker. Mike Jorda |
DAC | 2 |