In this paper we present a new communication network for on-chip interconnection. The network concentrates on small size communication link, non blocking effect, scalability. The network is based on a direct sequence code division multiple access (DS-CDMA) technique with a binary-truncated channel. By the truncation, the network drastically reduces data transfer lines. Our network architecture is largely divided into four modules: a CDMA-based network interface, an interconnection module, a synchronizer, and a hubnetwork interface. Especially the network includes a reverse channel for the efficiency of packet flow control. We guarantee the scalability of network by both a PN-code reuse and a hierarchical structure. We also decouple functional and communication tasks for scalability and utilize a modular architecture for flexibility. The network architecture is analyzed in terms of performance, area, and physical architecture. Our network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

The authors offer extended algebraic operations and strategies for se in algebraic approaches. A novel cube/array representation that directly shows some legal expressional variations from a minimal expression written in the conventional three symbol (0, 1, x) representation is defined, along with certain operations on those cube/arrays. Conversions between the new and conventional representations are explained. Division methods are presented that are based on expressions like those used to describe algebraic division but use more operations of Boolean algebra. Factoring on the new representations is explained. A multilevel logic synthesis algorithm with a control strategy is presented and compared with published systems.>

Designs of totally symmetric functions provided by logic synthesis systems have on average more than twice as many literals as best designs, while the designs of nonsymmetric functions have on average 20% more literals. A simple, but effective, heuristic method for synthesizing symmetric functions that detects and takes advantage of symmetry and is based on classic disjoint decomposition theory is fully developed from basic definitions. Functions are realized as Boolean networks with cost measured as the literal count of factored expressions. Programs based on the method almost always produce the best designs known to the authors. Two strategies for accepting decompositions are explored. They do produce different results in a few cases: examples are presented to show that neither always produces best designs. These programs are proposed as preprocessors for a comprehensive synthesis system.>