In recent years, intelligent processing of satellite videos has emerged as a significant research focus within the field of remote sensing, driven by the growing demand for enhanced spatial resolution. This need has led to increased interest in satellite video super-resolution (SVSR) algorithms, which aim to improve the quality of satellite imagery. However, many existing SVSR methods tend to neglect the global dependencies among frames in satellite videos, resulting in an incomplete utilization of spatio-temporal feature information. To tackle this issue, we propose a novel non-local spatio-temporal bidirectional recurrent network specifically designed for SVSR applications. Our approach employs a gate-guided deformable alignment module that effectively enhances feature alignment and fusion using a dynamic gating mechanism. This allows the network to adaptively focus on relevant features during the reconstruction process. Furthermore, we introduce a non-local spatio-temporal fusion module that integrates both temporal and spatial relationships over long sequences of frames, ensuring a comprehensive extraction of feature information. Through extensive experiments, our proposed method demonstrates superior performance compared to state-of-the-art SVSR techniques in terms of reconstruction quality. Additionally, it demonstrates outstanding performance in downstream satellite video applications, showcasing its potential in satellite video processing tasks. The source code is publicly available at https://github.com/Yu-Wang-0801/NSBRNet.

This article presents a 65-nm keyword spotting (KWS) chip that achieves 95.3% accuracy on 12-class tasks with 108.04-nJ/inference efficiency through cross-domain hardware-algorithm innovations. The unified fast Fourier transform (FFT)-butterfly-structured neural network (BFNet) accelerator fundamentally rethinks computational reuse: by replacing dense pointwise convolutions with butterfly-based sparse operations mirroring FFT’s dataflow, it slashes$6.3\times $multiply-accumulate (MAC) operations and halves parameter counts while preserving model expressivity. A 6-bit exponent-aware nonuniform quantization (EANUQ) scheme compresses weights, achieving a 25% reduction in storage while maintaining an accuracy loss of less than 0.01% with lightweight on-chip decoders. Hardware resource sharing extends beyond computation: Mel-filter-banks reuse fully-connected (FC) layer multipliers through decomposed 8-bit arithmetic, and FFT output buffers double as convolutional neural network (CNN) feature map memory. Measured at 0.65 V/600 kHz, the 0.58-$\text {mm}^{2}$core demonstrates$1.9\times $–$15.5\times $better energy efficiency than prior 65/28-nm implementations, with 14.82-ms end-to-end latency.

To date, many studies have been carried out for monitoring analytes in human perspiration with wearable sweat sensors, but few of them have done an in-depth investigation on the relationship between the acquired sensing data and human health status from a system scenario. In this article, we report a wearable smart sensor system (WS3), which can not only monitor the concentration of sodium ions in human perspiration but also predict the dehydration state of the human body. The proposed WS3 consists of an entire three-layer Internet of Things (IoT) structure. The perception layer includes a sweat sensor with a sensitivity of 60.3 ± 2 mV/decade, an analog front-end (AFE) with a signal amplification gain of 3, and a rechargeable 3.7-V Li-ion battery. The signal conditioning circuit can read the sodium ion concentration data obtained by the sweat sensor and wirelessly send it to the mobile phone APP in the application layer through Bluetooth. Besides, the mobile phone APP can exchange the data with the cloud server in the network layer through hypertext transfer protocol secure (HTTPS) requests, allowing the real-time post of concentration data and acquiring predicted dehydration states. Moreover, a lightweight deep-learning (DL) algorithm based on a Seq2Seq long short-term memory (LSTM) model with Luong attention is implemented in the cloud server, which achieves an overall accuracy of above 91% in the prediction of dehydration. The performance achieved by the WS3 combined with its high level of convenience and compactness makes it a promising wearable system for deployment in the IoT for daily human healthcare.

In this paper, we present an energy-efficient strong physical unclonable function (PUF) based on subthreshold inverters (STIs) that are regulated by a native NMOS transistor. Two groups of STIs can be dynamically regrouped to 4 stages according to the provided challenge, with each stage having different number of STIs connected in parallel. By adopting the first two stages as the entropy source and the last two stages for generating the PUF bits, the equivalent 4-stage STI chain can exhibit high reliability under largely varied temperature and supply voltage. Moreover, the proposed strong PUF implementation is validated using a standard 65-nm 1.2 V CMOS process. With the temperature and supply voltage changing from 0°C to 120°C and 0.7 V to 1.5 V, respectively, the worst-case bit error rate (BER) is reported to be 5.025%. Meanwhile, the energy consumption is simulated to be 0.26 pJ/bit at the maximum throughput of 10 Mb/s. Moreover, the proposed strong PUF shows high resilience to various machine learning (ML) attacks, including logistic regression, support vector machine and covariance matrix adaptation evolution strategy.

This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks. By introducing nonlinear operations through exploiting the random interconnections of delay stages, the proposed OIPUF can theoretically improve the physical unclonable function (PUF) security while consuming the same hardware resources as the conventional XOR arbiter PUF (XOR APUF). We further propose the metastability-detection (MD) arbiter to effectively improve the PUF reliability. Implemented on Xilinx Artix-7 field-programmable gate array, both the proposed (64,4)- and (64,8)-OIPUF demonstrate a good reliability and uniformity, with the proposed (64,8)-OIPUF showing a better uniqueness and strict avalanche criterion (SAC) performance. Measurement results also show that the proposed MD arbiter can reduce the bit error rate (BER) of the (64,4)- and (64,8)-OIPUF by$\geq 68\times $and$\geq 48\times $at up to 100 °C, respectively. Evaluated using the logistic regression (LR), artificial neural network (ANN), and covariance matrix adaptation-evolution strategy (CMA-ES) machine learning (ML) algorithms, the proposed (64,4)- and (64,8)-OIPUF can achieve a worst case prediction accuracy of 61.47% and 50.59% with up to 10M challenge–response pairs as training set, respectively, demonstrating a significant improvement over similar prior arts.

The IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) is the regional flagship conference of the IEEE Circuits and Systems Society (CASS) in Asia. This conference is a major international forum established by the IEEE Circuits and Systems Society for researchers to exchange their latest findings in circuits and systems. It covers a wide range of topics, including analog, mixed-signal, digital, communication, sensory, biomedical, power/energy, nonlinear, and artificial intelligence circuits and systems.

This paper presents a hardware-reuse strong physical unclonable function (PUF) based on the intrinsic transfer paths (TPs) of a conventional digital multiplier to achieve a strong modeling attack resilience. With the multiplier input employed as the PUF challenge and the path delay as the entropy source, all the possible valid propagation paths from distinct input/output pairs can serve as PUF primitives. We can quantize the path delay using a time-to-digital converter (TDC), and select the suitable TDC output bits as the PUF response. We further propose a lightweight dynamic obfuscation algorithm (DOA) and a secure mutual authentication protocol to counteract modeling attacks. The proposed strong PUF using a 32×32 multiplier as implemented in the Xilinx ZYNQ-7000 SoC features a total of 2048 intrinsic PUF primitives, while achieving a response stream (RS) with an average of 1024 responses per TDC output bit per challenge. WithBit(5) andBit(6) of the TDC output selected for PUF response generation, they demonstrate a measured reliability and uniqueness of up to 98.31% and 49.34%, respectively, with their excellent randomness performance as validated by the NIST SP800-22 tests. Under machine learning (ML)-based modeling attack with artificial neural network (ANN), the measured prediction accuracy of bothBit(5) andBit(6) can still be maintained at ~50% with a total of >200 million CRPs as the training set.

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries, such as logistics and freight transportation. To further promote RFID tags adoption, security, power consumption, and cost have always been issues of general concern. This article presents the first synergy of the RFID tag with embedded resistive RAM (RRAM) array and RRAM-based reconfigurable strong physical unclonable function (R-SPUF). The RRAM not only meets the mass storage and technology downscaling but also renders the ultralow-cost “1-cent RFID tag” more feasible. Moreover, the R-SPUF facilitates multiple initializations until a satisfactory distribution and has strong secure keys benefiting from its reconfigurability that improves both safety and reliability. The complete system operates at 13.56 MHz and is compliant with the ISO14443-A and ISO10373-6 (test) protocols. The RFID tag was fabricated on a 1.1-mm2 die based on the 0.18-$\mu \text{m}$CMOS process. Without resorting to the charge pumps for RRAM read–write operations, the total power consumption is as low as 52.3$\mu \text{W}$, of which the RRAM dissipates$16.2~\mu \text{W}$under a wireless power supply.

In this paper, we present a system-level model for an ambient temperature-compensated CMOS MEMS Thermal Flow (C2MTF) sensor. The system-level model is first validated by a computational fluid dynamics (CFD) model and is further used for a fully coupled simulation between the microstructure, heat transfer, and interface circuits. Correspondingly, a monolithically integrated C2MTF sensor is designed and optimized using a 0.18 μm 1P6M CMOS MEMS technology. The designed System on Chip (SoC) C2MTF sensor has a flow range of -10~10 m/s, and its highest sensitivity is 0.274 V/(m/s) with a system power consumption of less than 3.6 mW. In comparison with the more than 50% output drift for the uncompensated counterpart, the output drift of the designed C2MTF sensor is reduced to 7% under an ambient temperature of 0~50 °C. In addition, based on the proposed system-level model, the additional optimizations show that the output drift can be greatly reduced to 0.5%, by arranging another on-chip overheated temperature-regulating resistor Rcin the future, delicately.

Oscillator-based elementary true random number generator (TRNG) uses a slow jittery ring oscillator (RO) to sample a fast RO. The ROs are always on but most of the oscillatory cycles of the fast RO are not sampled into random bits. In this paper, a new lightweight TRNG design is proposed to minimize the power wasted by the superfluous oscillations. Random bits are extracted from both phases of the slow ROs to increase the throughput and the fast RO is activated only during the narrow transition time difference between two symmetrically designed slow ROs. The slow jittery ROs are implemented using current starved inverters biased in the weak inversion region to reduce their power consumption. Their jitter amplitudes are increased by lowering the oscillation frequency and reducing the drain current of the transistors. The narrow jittery pulse generated by the differential pair of slow ROs is quantized by the fastest three-stage RO. Two random bits from each phase of the jittery ROs can be extracted by using a gigahertz dynamic toggled D flip-flop counter to count the number of oscillatory cycles of the fast RO. The proposed TRNG is fabricated in a standard 65 nm 1.2 V CMOS process. Measurement results of the fabricated chips show that the proposed TRNG consumes merely$260~\mu \text{W}$at a bit rate of 52 Mbps. It outperforms the state-of-art on-chip jitter-based TRNGs with the best figure-of-merit of 5 pJ/bit and the smallest footprint of$366~\mu \text{m}^{2}$. Its generated bit sequence passes the statistical randomness tests including National Institute of Standards and Technology (NIST) test, Auto Correlation Factor (ACF) test and bias. The mean redundancy of the ten tested chips is measured to be less than 10−5bit/symbol.

This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of$6845\mu \text{m}^{2}$. Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across$1.06\sim 1.55V$and$- 30\sim 125^{\circ }\text{C}$, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using$80\times 80\times 80$artificial neural network (ANN) with 1M CPRs as training set.

In this paper, we present a novel physical unclonable function (PUF) based on dual entropy sources of a 2-transistor voltage reference (2T-VR) and a four-stage diode-clamped comparator. Featuring excellent stability over wide range of supply voltage and temperature, the proposed 2T-VR is constructed with one native transistor plus one PMOS transistor that are compensated to minimize its temperature coefficient. Moreover, different from most previous PUF implementations where a digital comparator with offset-cancellation is needed for digitizing the mismatched voltages/currents from the prior entropy stage, in this work, the customized diode-clamped comparator’s offset is well-exploited as an additional entropy source, which can be superposed on the above 2T-VR-based entropy to significantly elevate the whole PUF structure’s reliability. Besides, a near zero-overhead in-cell entropy sign based stabilization (ESS) scheme is proposed to further enhance the reliability by stabilizing the scenario with the dual entropy sources having opposite signs. The designed dual-entropy-superposed PUF is fabricated using a 65-nm standard CMOS process, and its excellent randomness is validated using the widely-accepted National Institute of Standards and Technology (NIST) PUB 800-22/800-90B and autocorrelation function (ACF) test tools. With the test chips repeatedly challenged at normal condition up to 4000 times, the measured native bit error rate (BER) and unstable bits are reported to be 0.16% and 1.3%, respectively. Moreover, with the operating temperature changing from −50°C to 130°C and the supply voltage changing from 0.8 V to 1.4 V, the native BER’s VT sensitivities without stabilization are measured to be 0.195%/10°C and 0.651%/0.1 V, respectively, which can be further reduced by$4.5\times $and$1.5\times $with the proposed ESS scheme applied.

Developing efficient metal-organic framework (MOF) based nanocomposite sensor with superior performance for fast, sensitive and selective detection of ammonia (NH3) is essential for environmental protection and human health. This work reports synthesis of Pd-Co@IRMOF- 1 nanocomposite based gas sensor for the detection/sensing of ammonia (NH3) at room temperature. The successful synthesis of Pd-Co@IRMOF-1 nanocomposite was confirmed with spectroscopic and structural characterizations. Unlike earlier realizations, the fabricated Pd-Co@IRMOF-1 nanocomposite based sensor showed notable detection sensitivity for NH3 at concentrations down to 1ppm level. Distinctly, the MOF based nanocomposite sensor exhibited the excellent sensitivity and long-time stability to NH3. In contrast to other reported MOFs, Pd-Co@IRMOF-1 showed remarkable selectivity towards ammonia in comparison to formaldehyde, ethanol, acetone, Isopropyl alcohol and benzene. The Pd-Co@IRMOF-1 based sensor exhibited excellent performance for sensing of ammonia which can be helpful for future in wearable sensor device applications.

In this article, a novel subthreshold voltage reference (VR)-based physical unclonable function (PUF) is presented. With two native nMOS transistors stacked on top for providing bias current and two bottom low threshold voltage (LVT) nMOS transistors forming the self-cascode MOSFETs structure, a 4T all-MOSFET VR is proposed, which features low power consumption and high stability under largely varied VT conditions for the wide range of Internet of Things (IoT) applications. By integrating a pair of the proposed VRs and a digital voltage comparator in each PUF cell, the mismatched output voltages of the VR pair can be locally compared and digitized immediately with the system's power on, leading to ultrashort signal path and maximized immunity to the influence of temporal noise. Fabricated using standard 0.18- μm CMOS process, the proposed PUF design is validated based on extensive measurement results of 20 PUF chips. By passing the widely exploited bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test, the proposed PUF's excellent randomness is well-verified. In addition, the uniqueness is measured to be 49.92%, and the bit error rate (BER) sensitivities in terms of BER per 10 °C and BER per 0.1 V are averaged and reported to be 0.39% and 0.26%, for the temperature range of -40 °C-120 °C and supply voltage range of 1.2-1.8 V, respectively. Moreover, by operating the proposed implementation at a throughput of 50 Mb/s, the measured overall energy consumption is reported to be as low as 163 fJ/bit.

In this paper, we present an ultra-low power true random number generator (TRNG) based on ring oscillator (RO) with current-biased inverters. Random numbers are extracted by symmetrically designed arbiter depending on the jitter-noise-caused phase difference of a pair of ROs. Using a bias transistor shared by 16 inverters (8 for each RO), we can obtain a virtual power supply lower than VDD(denoted as V VDD) and a subthreshold bias current to increase the oscillation frequency while ensuring high randomness. In addition, power consumption is significantly lowered by using V VDDto reduce the amplitude of oscillation. Moreover, V VDDcan be designed with high temperature and supply voltage stability by optimizing the transistor sizes, which allows the proposed implementation to generate random numbers and pass both NIST and auto-correlation test suites over wide ranges of supply voltage (1.0V~1.4V) and temperature (0°C~120°C). The proposed TRNG is implemented using standard 65nm CMOS process, with the bit generation rate and energy efficiency reported to be 169Mbps and 30fJ/bit, respectively (1.2V and 27°C).

This paper presents a digital N × N multiplier-based multi-bit strong physical unclonable function (PUF), which utilize the intrinsic path delay of the multiplier to achieve an approximated 1 : 2N2average challenge-to-response extraction to effectively increase the number of PUF responses. The PUF Extractor triggers the digital multiplier, and further processes the multiplier intrinsic path delay through a time-to-digital converter (TDC). Implemented with Xilinx Artix-7 FPGAs using the automatic place and route function, the proposed strong PUF demonstrates a 64-bit challenge with 32-bit multipliers with an extra level of unpredictability for counterfeiting model-based machine learning attack. With an average of 1:2048 responses per challenge, measurement results show that the uniqueness is 53.16%, and the stability of up to 95.54%, respectively.

In this paper, we present a novel multiple-stage amplifier chain based strong physical unclonable function (PUF) with low power and energy consumption. Based on the proposed two-dimensional subthreshold amplifier array, 12 different amplifiers can be selected through the analog multiplexer at each column. As a result, a 12-stage amplifier chain can be formed by applying different challenges to the aforesaid analog multiplexers with a linear feedback shift register (LFSR). Due to the inevitable process variation, the output voltage of the amplifier chain's last stage varies depending on the various combinations of the selected amplifiers, whose number features an exponential relationship with the size of the adopted amplifier array. By using 65nm standard CMOS process, the proposed strong PUF implementation is validated with high reliability and randomness. According to our extensive simulation results, the averaged bit error rate (BER) per 10°C and BER per 0.1V are calculated to be 3.15% and 3.85% for the operating temperature range of -20°C~120°C and supply voltage range of 0.9V~1.4V, respectively. Meanwhile, the proposed strong PUF's high randomness is also verified by passing both the NIST and auto-correlation function (ACF) test suites. Moreover, featuring an excellent uniqueness of 49.54%, the overall power consumption is simulated to be 0.128μW at the throughput of 0.02Mb/s, which corresponds to an energy consumption as low as 6.4pJ/bit.

As surveillance footage plays an increasingly significant role in law enforcement, it is imperative to ensure the integrity of recorded video data and the authenticity of its originator, and instill situation awareness into these monitoring systems with a fidelity record of the incidents. Unfortunately, existing frame-based networked surveillance systems could only partially fulfill these requirements. The emerging Dynamic Vision Sensor (DVS) sheds new light on solving this problem with its completely different sensor design, i.e., DVS responds only to temporal intensity change and records only sparse asynchronous address-events with precise timing information. Motivated by the reduced data size of activities and the prevention of privacy intrusion of subjects under surveillance as well as other appealing attributes, this work introduces the first event-driven physical unclonable function (Ed-PUF) system to fill the forensic gap of simultaneously authenticating the event data integrity and source camera identity for reactive monitoring by DVS camera. New DVS sensor architecture is proposed with negligible modifications made to the original DVS pixel. The Ed-PUF response bit can only be triggered by and uniquely dependent on the asynchronous addressed event without being interfered by the simultaneous firing of other address events. Address event streams are securely transmitted with an event package tag created by a keyed hash-based message authentication code with the key being the Ed-PUF response. A secure protocol to authenticate the identity of DVS camera and the integrity of address events transmitted through cellular network is also proposed. A camera lock is embedded to protect against severing and splicing the inter-chip connectivity within the camera for raw PUF responses. The proposed system is evaluated using raw PUF data obtained by post-layout Monte Carlo simulation in UMC 180nm technology and real event stream captured by a DVS camera. The proposed Ed-PUF has been demonstrated to have excellent uniqueness, randomness and reliability. Collision test is also conducted to show that the quality of DVS imaging is not compromised. Besides keeping the hardware/power/timing overheads low, the proposed scheme is also analyzed to be resilient against multiple attack scenarios.

This paper presents a fast and effective polarization image demosaicking algorithm, which explores inter-channel dependency of Stokes parameters for the minimization of residual aliasing artifacts after cubic spline interpolation. A guided filtering approach is used for denoising. An optimization based on the confidence level of the aforementioned guided filtering, the correlations between the demosaicked image and input, as well as the total intensity, angle and degree of linear polarization, is constructed and solved with Newton's method. Experimental results demonstrate that the proposed algorithm can surpass the existing methods in terms of both objective root mean squared error and structural similarity index by at least 36.0% and 3.4%, respectively, and by close visual inspection of the clarity of objects in the angle and degree of linear polarization images. The proposed algorithm consists of only convolutions and element-wise operations, making it fast and parallelizable for efficient GPU acceleration. An image of size 512 × 612 × 4 can be processed within 10 s on i7-6700k CPU, and gains further 5 times speedup with M4000M GPU.

In this article, a compact physical unclonable function (PUF) based on cross-coupled comparator is presented. Featuring a positive feedback response generation mechanism, the mismatch in analog signals between the cross-coupled transistor pair is quickly amplified to prevent its polarity from flipping by the temporal noise. The rapid enlargement of noise margin by the sense amplifier also contributes to stabilizing the response against supply voltage variations. To improve its temperature stability, the counteracting effect of complementary-to-absolutetemperature (CTAT) and proportional-to-absolute-temperature (PTAT) drives are considered in sizing the bit cell transistors. The proposed design is fabricated in a standard 65-nm CMOS process. The bit cell occupies an area of only 4.38 μm2(i.e., 1036 F2), and the overall PUF chip consumes 2.98 pJ/bit at the throughput of 8 Mb/s, of which only 1.61 pJ/bit is due to the PUF's core. With the uniqueness measured to be 49.53%, the unpredictability of the fabricated PUF chips is validated by autocorrelation function and NIST randomness tests. Compared with the state-of-the-art implementations, the proposed PUF has the lowest native response instability of 1.46% with 500 repeated PUF readouts at 27 °C and 1.2 V. By varying the operating temperature from -50 °C to 150 °C in a step size of 10 °C and the supply voltage from 1.0 to 1.4 V in a step size of 0.1 V simultaneously, the average reliability of the proposed PUF obtained from the 2-D plot of all operating conditions is found to be 96.87% without correction and 99.31% with spatial majority voting (SMV).

In this paper, a novel in-pixel event-driven physical unclonable function (PUF) is presented for the rapidly developed CMOS dynamic vision sensor (DVS). Different from traditional widely reported PUF implementations with additional dedicated silicon area, power consumption and peripheral circuitries, the proposed implementation extracts PUF based on the original gain amplifier existing in the mainstream DVS pixel, which is necessary to amplify the front-end logarithmic photoreceptor's relatively weak output signal, according to the ratio of the in-pixel capacitor pair. With any ON/OFF event generated and the corresponding DVS pixel fired asynchronously, the DVS pixel's own gain amplifier will be reset in order to capture the next possible event. Due to the inevitable variation of the semiconductor fabrication process, the reset voltages of different DVS pixels' gain amplifiers are slightly different. A bidirectional counter based analog-to-digital converter is customized to digitize the successively fired pixel pair with the sign bit representing the PUF bit (i.e. the reset voltages' difference). Moreover, the proposed implementation is validated using a standard 0.18μm CMOS process in Cadence. According to the extensive post-layout simulation results, the uniqueness is calculated to be 49.97%. With the operating temperature varying from -40°C to 120°C and supply voltage varying from 1.7V to 2.1V, the worst-case reliability is reported to be 96.48% and 97.27%, respectively. Meanwhile, its superior randomness is also verified using the NIST test suite.

In this paper, we present a novel physical unclonable function (PUF) structure based on 2T voltage reference and diode-clamped comparator. The proposed PUF implementation includes an array of the aforesaid 2T voltage references with same transistor size and layout design. Meanwhile, the output voltage variation mainly caused by the CMOS process variation can be well-extracted by the adopted diode-clamped comparator to generate a digital bit stream (256 bit) with excellent randomness. By utilizing the sub-threshold 2T voltage reference's superior stability to the environmental variations (e.g. operating temperature, supply voltage), the proposed implementation exhibits ultra-high reliability against wide-range operating temperature and supply voltage. This design is validated by our extensive post-layout simulations based on 65nm standard CMOS process, the average reliability is reported to be 99.88% and 99.37% for the operating temperature ranging from -40°C to 120°C and the supply voltage ranging from 0.8V to 1.8V, respectively. In addition, the overall power consumption is reduced to 3.1μW at a throughput of 10 Mb/s. Moreover, the superior unpredictability (i.e. randomness) of this design is verified by passing both the auto-correlation test and NIST randomness test.

In this paper, a current mode physical unclonable function (PUF) based on the winner-take-all (WTA) scheme is presented. By using the process variation of the single transistor in the current mirror array, digital values with superior randomness can be produced. With the proposed WTA scheme, the time needed to acquire the currents' difference is significantly reduced. Meanwhile, the overall power consumption is also greatly lowered with the simplified peripheral circuitry. Moreover, unstable bit replacement circuitry is customized to remove the unstable bit caused by WTA's mismatch, which further improves the reliability of our proposed PUF. According to the simulation results using standard 65nm CMOS process, the proposed unstable replacement circuitry can replace up to 12.07% of the unstable bits. In addition, the superior averaged temperature reliability of the proposed implementation is 99.53% from -20° C to 100°C, with the overall power consumption as low as 892nW.

Low power, lightweight and robust physical unclonable function (PUF) is a sought-after for IoT device identification/authentication. This paper presents a low power PUF design with high reliability against temperature and supply voltage variations. A response bit is extracted by comparing a pair of identically designed subthreshold voltage references. The voltage difference due to device mismatch is digitized and registered in a bidirectional counter, which can be used to identify and filter out the unstable response bits. The readout circuit works in tandem with the proposed double sampling technique to reduce the bias of components that are not the main entropy source of response bits. The proposed design is evaluated by extensive simulation using standard 65 nm CMOS process. It consumes merely 0.16 pJ/bit. The simulated uniqueness is an almost ideal 50.03%. Due to the intrinsic stability of voltage references, the reliability of its native response is 98.17% for the supply voltage variation from 1 V to 1.4 V and 97.60% for the temperature variation from 0 ° C to 80 °C. The generated response bitstream has passed both the autocorrelation test and NIST randomness test.

This paper presents a novel K times singular value decomposition (K-SVD) based denoising algorithm for the division-of-focal-plane (DoFP) polarization image sensors. In the proposed implementation, the input DoFP image can be expressed by the optimum sparse combination of the dictionary elements via K-SVD and orthogonal matching pursuit (OMP) algorithms. As a result, this implementation is capable of eliminating the Gaussian noise significantly and well-preserving the details and edges of the target DoFP image. Our extensive experimental results on various test images show that the proposed algorithm yields better visual quality and maintains a lower PSNR value while compared with a wide range of previous implementations.

In this paper, we present a novel smoothness-based interpolation algorithm for the division of focal plane Polarimeters (DoFP). By calculating the divided blocks' variance that represents their local smoothness, the proposed algorithm well-balances between the traditional bilinear and bicubic interpolation algorithms. In addition, compared with the previously reported gradient-based interpolation algorithm which only indicates the image's directional change along 0°, 90°, 45° and 135°, the presented smoothness-based algorithm covers the variations along all the possible directions, leading to more accurate selection between the bilinear and bicubic algorithms. According to our extensive simulation results, the proposed implementation exhibits the lowest mean square error (MSE) for the test images among all the previously reported algorithms, including bilinear, bicubic and gradient-based interpolation algorithms.

The level shifters are crucial primitives in the multi-supply voltage circuits and systems. In this paper, an energy-efficient level shifter is proposed to achieve the conversion from the subthreshold voltage to the above threshold voltage. It is a hybrid structure consisting of the Wilson current mirror and the cross-coupled level shifter. By addressing the voltage drop issue of the level shifter based on the Wilson current mirror, the leakage power is significantly reduced, with the advantage of wide input voltage range for the Wilson current mirror level shifter well-preserved. In addition, the multi-threshold CMOS (MTCMOS) technology is employed to provide more flexibility for our ultra-low power design. The reported simulation results using 65 nm CMOS process validate our proposed implementation and an ultra-low power consumption of 19.44 fJ per conversion from 0.2 V to 1.2 V at 1 MHz is achieved without the need of any intermediate power supply.

In this paper, we present a novel physical unclonable function (PUF) based on time-domain current difference measurement. By employing the aforesaid simplified current-mode PUF architecture, the proposed implementation completely removes the need of complex error correction circuitry, which is widely adopted in the previously demonstrated implementations. This leads to significant reduction of both the overall power consumption and the required chip area. In addition, the proposed implementation exhibits a superior bit error rate (BER) as low as 0 for the typical case scenario and 1.56% for the worst case scenario, respectively. Featuring an ultra-low power consumption of 11.29μW and an averaged silicon area of 13310μm2, the proposed implementation is validated by our reported extensive post-layout simulation results with UMC 0.18μm standard complementary-metal-oxide-semiconductor (CMOS) technology.

In this paper, a novel CMOS-compatible ZnO nanocomb-based gas sensor is presented. Compared with previously reported implementations, the proposed ZnO nanocombs feature multiple conducting channels and much larger effective sensing area, both of which result in dramatically improved sensitivity (6.54 for 250 ppm CO), response time (3.4 min) and recovery time (0.24 min). In addition, by operating the gas sensor at room temperature, additional power-hungry heating components inevitable in traditional implementations are completely removed. This not only leads to low power consumption, but also avoids the high-temperature-caused reliability degradation when integrated with CMOS circuitry.

In this paper, we present a low cost CMOS polarimetric ophthalmoscope scheme enabling the capture of the retinal abnormalities that are unique to cerebral malaria. The proposed technology, which can be integrated into cellphones, offers the basis for quick and non-invasive screening of cerebral malaria. In addition, we report a high quality micropolarizer array for the proposed polarimetric ophthalmoscope, exploiting “guest-host” interactions in liquid crystals. With dichroic azodye-1 (AD1) molecules as the “guest” and nematic liquid crystal (NLC) molecules as the “host”, we demonstrate a better control of the molecular orientation of the “guest”, which in turn results in a ~25% increase of the major principal transmittance and a 139% increase of the peak extinction ratio. The proposed micropolarizer fabrication technology is simple and cost-effective, requiring only selective photo-patterning of a “guest-host” polymer spincoated over the image sensor.

In this paper, we propose a liquid-crystal mi-cropolarimeter (LCMP) array with high spatial resolution for real-time linear and circular polarization imaging in visible spectrum. LCMPs for extracting 0°, 90° linearly and right-handed circularly polarized components of incident light are implemented by micro-patterning a liquid crystal (LC) layer on top of a 45° oriented ultra-thin metal-wire-grid polarizer (MWGP). A compact LCMP pitch of 5μm × 5μm is achieved with sulfonic-dye-1 (SD1) as the LC alignment material. In addition, these micron-scale LCMPs feature ~5μm overall thickness and ~1100 extinction ratio. Reported experimental results validate the concept of real-time linear and circular polarization image sensing and processing with targets illuminated by collimated artificial light.