Localized air pollution need to be tackle in dense urban area. This paper presents a mobile sensor platform aiming at high quality air particle matter measurements in a metropolis. Its installation on a bus service enables a cost-effective sensor deployment and the integration of computing power at the edge.

We present a tool for graph coverage with a fleet of UAVs. The UAVs must achieve the coverage of an area under the constraint of staying connected with the base, where the mission supervisor starts the plan. With an OpenStreetMap interface, the user is able to choose a specific location on which the mission needs to be generated and observes the resulting plan being executed.

It is an honor to introduce the technical program for the 22nd International Conference on Parallel Architectures and Compilation Techniques. The conference has become a premier forum for presenting new contributions in computer architecture and compiler technology. It allows both communities to interact and exchange.

Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper describes the project and provides an overview of the research carried out by the TERAFLUX consortium.

Multicore processor architectures provide huge computation power by leveraging multiple levels of parallelism. However, it is non-trivial to orchestrate computational and memory resources allocation on the multicore platform. In this paper, we model the resources allocation for multicores as an optimization space, including variant selection, grouping and PE assignment. Finding efficient parallelization schemes for a multi-task program is to explore this search space. In order to accelerate the space exploration, we adapt genetic algorithm to find out the performance optimal solutions. Experiments are conducted on the Cell BE using two benchmarks. Compared to exhaustive enumeration, the intelligent search based on genetic algorithm can derive good parallelization schemes in very short time.

Computing the actions of Wilson-Dirac operator contributes most of the CPU time for the grand challenge problem of simulating Lattice Quantum Chromodynamics (Lattice QCD). This routine exhibits many challenges in implementation on most computational environments because of the multiple patterns of accessing the same data, making it difficult to align the data efficiently at compile time. Additionally, the low computation to memory access ratio makes this computation bounded by the memory bandwidth and the memory latency.

The Automatic Speculative Thread Extractor, ASTEX, addresses the problem of partitioning C code into threads at compile time in order to map them onto System on Chip (SoC). The startpoint of thread extraction is to find the code region to implement as thread. In ASTEX it is based on program hot-paths detection. Then ASTEX construct a thread speculative model for each hot-path. Since ASTEX, contrary to previous work, doesn't assume shared memory, the speculation is performed on control flow and data layout also. The output is a set of threads characterized by their execution time, the code coverage, the amount of memory and communication required, etc. Our Experiments show that the approach is able to capture and to characterize the main computation kernels of embedded applications and how the hot path detection algorithm paremeter influence the final output layout.

Abstract Embedded systems are increasingly expected to provide good performance at low cost. As the characteristics of compiled code can have an impact on the overall cost of an embedded system, a compilation strategy must be cost aware as well as achieve high performance. As one major factor for system cost is memory size, code size becomes an important issue in code generation. Thus, cost‐effective optimization strategies that are able to perform a good trade‐off between code size and performance improvement are needed. In this paper, we propose a novel method based on Integer Linear Programming for computing efficient unroll factors for collections of loop nests with control over code size and side‐effects of the transformation. We define a notion of trade‐off between code size and performance. Experiments on the Philips Trimedia show that our method achieves excellent trade‐offs. Copyright © 2006 John Wiley & Sons, Ltd.

Branch prediction mechanisms are becoming commonplace within current generation processors. Dynamic branch predictors, albeit able to predict branches quite accurately in average, are becoming increasingly complex. Thus, determining their worst-case behavior, which is highly recommended for real-time applications, is getting increasingly difficult and error-prone, and may even be soon impossible for the most complex branch predictors. In contrast, static branch predictors are inherently predictable, to the detriment of a lower prediction accuracy. In this paper, we propose a WCET-oriented static branch prediction scheme. Unlike related work on compiler-directed static branch prediction, our scheme does not address program average-case performance (i.e. average-case branch misprediction rate) but addresses worst-case program performance instead (i.e. branch mispredictions which impact programs WCET estimates). Experimental results on a PowerPC 7451 architecture show that the estimated WCET can be decreased by up to 21 % (with an average improvement of 15%) as compared with the method where all branches are conservatively considered mispredicted. Our scheme, although applicable to any processor with support for static branch prediction, is specially suited to processors with complex dynamic predictors, for which safe and tight WCET estimate methods do not exist.

The design of an embedded system is often heavily constrained by its performance objective and budget envelope. Software code compression may reduce the instruction memory space and then the overall cost of the system. However, it may also induce performance degradation. Previous studies proposed selective code compression using profile information in order to reduce the performance penalty. In this paper, we go one step further. We propose a software-only compression system, called SCS, that automatically finds trade-offs between code size and performance. Through an iterative approach, SCS automatically determines which functions to be compressed given a performance constraint and/or a code size constraint in order to guarantee a minimal performance and a maximal code size for an application. Experimentations illustrate that even with a non-optimal software decompression approach, SCS achieves a high compression rate with a minimal performance degradation.

This paper evaluates managing the processor's datapath-width at the compiler level by means of exploiting dynamic narrow-width operands. We capitalize on the large occurrence of these operands in multimedia programs to build static narrow-width regions that may be directly exposed to the compiler. We propose to augment the ISA with instructions directly exposing the datapath and the register widths to the compiler. Simple exception management allows this exposition to be only speculative. In this way, we permit the software to speculatively accommodate the execution of a program on a narrower datapath-width in order to save energy. For this purpose, we introduce a novel register file organization, the byte-slice register file, which allows the width of the register file to be dynamically reconfigured, providing both static and dynamic energy savings. We show that by combining the advantages of the byte-slice register file with the advantages provided by clock-gating the datapath on a per-region basis, up to 17% of the datapath dynamic energy can be saved, while a 22% reduction of the register file static energy is achieved.

Abstract In this paper, we propose SWARP, a retargetable preprocessor for exploiting multimedia instructions. The system mixes loop distribution, unrolling and pattern matching to exploit complex multimedia instructions. Contrary to all available systems, it can be extended at the user level. Using with a TriMedia processor we show that our system achieves important good code quality with a set of frequently used loop kernels for multimedia applications. Copyright © 2004 John Wiley & Sons, Ltd.

For most parallel and high performance systems, tuning guides provide the users with advices to optimize the execution time of their programs. Execution time may be very sensitive to small program changes. Such modifications may be local (on loop) or global (data structures and layout).

OpenMP was recently proposed by a group of vendors as a programming model for shared memory parallel architectures. The growing popularity of such systems, and the rapid availability of product-strength compilers for OpenMP, seem to guarantee a broad take-up of this paradigm if appropriate tools for application development can be provided. POST is an EU-funded project that is developing a product, based on FORESYS from Simulog, which aims to reduce the human effort involved in the creation of OpenMP code. Additional research within the project focuses on alternative techniques to support OpenMP application development that target a broad variety of users. Functionality ranges from fully automatic strategies for novice users, the provision of parallelization hints, and step-by-step strategies for porting code, to a range of transformations and source code analyses that may be used by experts, including the ability to create application-specific transformations. The work is accompanied by the development of OpenMP versions of several industrial applications. Copyright © 2000 John Wiley & Sons, Ltd.

This paper presents an overview of the activities carried out within the ESPRIT project OCEANS whose objective is to investigate and develop advanced compiler infrastructure for embedded VLIW processors. This combines high and low-level optimisation approaches within an iterative framework for compilation. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Article Free Access Share on A user level program transformation tool Authors: François Bodin IRISA-INRIA, Campus de Beaulieu, 35042 Rennes, France IRISA-INRIA, Campus de Beaulieu, 35042 Rennes, FranceView Profile , Yann Mével IRISA-INRIA, Campus de Beaulieu, 35042 Rennes, France IRISA-INRIA, Campus de Beaulieu, 35042 Rennes, FranceView Profile , René Quiniou IRISA-INRIA, Campus de Beaulieu, 35042 Rennes, France IRISA-INRIA, Campus de Beaulieu, 35042 Rennes, FranceView Profile Authors Info & Claims ICS '98: Proceedings of the 12th international conference on SupercomputingJuly 1998Pages 180–187https://doi.org/10.1145/277830.277868Published:13 July 1998Publication History 16citation393DownloadsMetricsTotal Citations16Total Downloads393Last 12 Months24Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Performance tuning becomes harder as computer technology advances. One of the factors is the increasing complexity of memory hierarchies. Most modern machines now use at least one level of cache memory. To reduce execution stalls, cache misses must be very low. Software techniques used to improve locality have been developed for numerical codes, such as loop blocking and copying. Unfortunately, the behavior of direct mapped and set associative caches is still erratic when large data arrays are accessed. Execution time can vary drastically for the same loop kernel depending on uncontrolled factors such as array leading size. The only software method available to improve execution time stability is the copying of frequently used data, which is costly in execution time. Users are not usually cache organization experts. They are not aware of such phenomena and have no control over it. In this paper, we show that the recently proposed four-way skewed associative cache yields very stable execution times and good average miss ratios on blocked algorithms. As a result, execution time is faster and much more predictable than with conventional caches. It is therefore possible to use larger block sizes in blocked algorithms, which will further reduce blocking overhead costs.

No abstract available.

Performance tuning becomes harder as computer technology advances. One of the factors is the increasing complexity of memory hierarchies. Most modern machines now use at least one level of cache memory. To reduce execution stalls, cache misses must be very low. Software techniques used to improve locality have been developped for numerical codes, such as loop blocking and copying. Unfortunately, the behavior of direct mapped and set associative caches is still erratic when large numerical data is accessed. Execution time can vary drasticly for the same loop kernel depending on uncontrolled factors such as array leading size. The only software method available to improve execution time stability is the copying of frequently used data, which is costly in execution time. Users are not usually cache organisation experts. They are not aware of such phenomena, and have no control over it.

No abstract available.

A programming environment for distributed memory parallel computers, consisting of a Fortran 77 compiler enhanced with directives to specify parallelism, is introduced. These directives are used to specify shared data structures and parallel loops. Shared data structures are implemented using the KOAN shared virtual memory that is available on an Intel iPSC/2 computer. Preliminary results obtained with the first prototype of the compiler are presented.

Long Instruction Word (LIW) architectures exploit parallelism between various functional units. In order to produce efficient code for such an architecture, the microcode compiler will have to expose a relatively large degree of fine grain parallelism and it will have to take into account the fine level characteristics of the architecture. This paper aims at describing a microcode compiler developed at IRISA for such architectures. After a brief overview of the compilation process, we focus on loop scheduling techniques. The software pipelining algorithm is firstly described. Then a new unrolling-based optimization algorithm is introduced and compared to the classical software pipelining algorithm. This algorithm differs from the traditional loop unrolling algorithm because the unrolling of the loop is only used to find a cyclic scheduling of the loop, then this scheduling allows a software pipelining to be constructed.

The techniques of “load/store” memory reference modeling is based on deriving performance characteristics of the memory architecture of a computer by looking at the behavior of simple sequences of load, store and nop (null operation) instructions. The resulting data base can be used to match load/store templates against algorithm kernels to predict performance or as a source of data for testing analytical models of the architecture. In this paper we study the BBN GP1000 parallel processing system. We show how to build a subset of the load/store kernels needed to characterize the machine and illustrate the behavior of a simple model based on the data.

This paper aims at describing a high-performance programmable pipeline architecture consisting of a linear array of PCS processors. The PCS processor which is capable of performing 20 million floating-point operations per second (20 MFLOPS) has been built from off-the-shelf chips on a wire-wrapped board. The prototype processor is attached to a SUN-3 workstation.Efficient microcode is generated using the microcode compiler that has been designed and implemented. The microcode optimization includes microcode compaction and loop optimization using the software pipelining technique. Another loop optimization technique based on the unrolling is also outlined. Preliminary results obtained on vector benchmarks are given.