Spin-transfer torque magnetic RAM (STTMRAM) is a promising candidate to replace SRAM due to its beneficial features of non-volatility, higher density, and zero leakage power. To further increase the data density, multi-level cell (MLC) STT-MRAM, which can store two bits per cell has been proposed. However, it has to conquer the two-step transition (TT) threats for some state transitions because writing the hard domain of a cell also writes the soft domain to the same value. The main drawbacks of TT are higher power consumption and a performance penalty. To address this issue, this paper proposes a novel two-step transition zeroization (TSTZ) technique that can completely eliminate two-step transitions. TSTZ is basically a ternary encoding technique where each MLC cell stores a ternary digit. The ternary digits 0,1, and 2 are encoded into cell states 00, 01/10, and 11, respectively. Since only three states of an MLC cell are used at a time, TSTZ eliminates TTs and significantly reduces the read error rate. Corresponding hardware architectures for encoding and decoding have also been proposed. The space overhead incurred is about 33%, the lowest among existing techniques. Power consumption and lifetime can be improved by 12% and 22.1% respectively. Moreover, the read error rate can be reduced from the original 8.24% to 0.75%.

Built-in self-repair (BISR) techniques and error correction codes (ECC) are widely used for repairing permanent faults and transient faults of flash memory, respectively. The main drawbacks of these techniques include the large granularity of spare usage and the uniform ECC protection capabilities. To cure these dilemmas, a novel Integrated Progressive BISR (IPBISR) technique which integrates fine-grained BISR (FGBISR) and progressive ECC (PECC) technique is proposed in this paper. Repairable fault types (RFTs) are first presented such that spare replacement can be conducted at the word-, page-, column-, and NAND block levels. We also propose the Complete March-FT (March-CFT) test algorithm which can also detect the read disturb faults not covered by the conventional March-FT algorithm. Besides the conventional fault models, the passability of each flash memory cell can also be tested. Therefore, the generated syndrome of March-CFT can be used to determine the RFTs of the detected faults. Instead of merely using redundancies for repairing different RTFs, we also incorporate PECC technique in IPBISR for repairing faulty cells occurred during manufacturing and field usage. PECC can progressively enhance the protection levels when the current protection capability is exhausted. A simulator is implemented for evaluating the novelties of the proposed IPBISR technique. Experimental results show that repair rate, yield, and reliability can be enhanced greatly with negligible hardware overhead.

Fault securing techniques based on address remapping (AR) for RRAM are proposed in this paper. We first classify the traditional RRAM fault models into 1-maskable fault and the 0-maskable fault types based on their fault effects. Therefore, the fault effects of most faulty cells can be masked before subject to the usage of ECC and hardware redundancies. Therefore, the burden of ECC and hardware redundancy techniques can be greatly reduced. The corresponding test and repair flow is also presented. A simulator is developed to evaluate the hardware overhead, repair rate, yield, and reliability. According to experimental results, we can enhance these measures significantly with almost negligible hardware overhead.

Resistive open defects may occur at interconnects between a printed circuit board and ICs in solder process. An enhanced test method in final tests and a built-in test circuit are proposed to detect resistive open defects of small resistance with relaxation oscillator embedded in ICs in this paper. It is examined by Spice simulations what resistive open defects can be detected. The results show that resistive open defects of 23.4 Ω and above are detected by the test method in a test speed of 1 MHz per an interconnect.

Deep neural networks (DNNs) are being widely used in smart appliances, face recognition and autonomous driving. The trained weight data are usually stored in flash memory which suffers from reliability and endurance issues. Owing to the inherent error tolerability for DNN applications, address remapping techniques are proposed for protecting weight data stored in flash memory. Bit significances are first analyzed and then a weight transposer is proposed for remapping significant weight bits to fault-free or much reliable flash cells. A bipartite graph model is developed for modeling address remapping. The corresponding hardware architectures for address remapping are also proposed. We use the deep learning framework pytorch for evaluating inference accuracy for different DNN models. Experimental results show that based on 0.01 % injected BER in the weight data, the accuracy losses of widely used DNN models are less than 1 % with negligible hardware overhead.

High power consumption in LSI testing may cause excessive IR-drop. When IR-drop becomes excessive, it causes excessive delay, resulting in test malfunction (over-testing). Excessive IR-drop does not occur in the entire area of a circuit, but in certain areas where a large number of switching activities occur (such areas are called hotspots in this work). In order to avoid test malfunction, it is important to develop a method to reduce or control IR-drop in the hotspots. Locating hotspots is a necessary technique to reduce or control IR-drop effectively and efficiently. In this work, we propose a method to locate hotspots in a logic circuit by switching probability calculation. Experimental results for IWLS2005 OpenCores circuits demonstrate the proposed method can support to locate hotspots.

Built-in self-repair (BISR) techniques has been considered as the most cost-effective solution for enhancing yield and reliability of NAND flash memory. Owing to the inherent architecture of NAND flash memory, conventional BISR techniques use spare columns and NAND blocks as the basic replacement elements. These techniques can be categorized as the coarse-grained BISR techniques (CGBISR). It is evident that the efficiency of spare usage is very low. To cure this dilemma, fine-grained BISR (FGBISR) techniques are proposed in this paper. We first exploit the fault behaviors at the circuit level and derive novel and concise repairable fault types (RFTs) for the widely used flash memory fault models. The proposed RFTs include bit-, page-, column-, and NAND block-repairable faults. Therefore, FGBISR can conduct repairing at the fine-grained levels for improving repair efficiency. We also provide efficient redundancy analysis algorithms suitable for VLSI implementation based on the RFTs. The corresponding FGBISR architectures and repair flow are also proposed. A simulator was developed for evaluating repair rate, yield, reliability, and hardware overhead. Experimental results show that repair rate, yield, and reliability can be raised significantly with negligible hardware overhead.

Deep neural networks (DNNs) are being widely used in smart appliances, face recognition and autonomous driving. The trained weight data are usually stored in flash memory which suffers from reliability and endurance issues. Owing to the inherent error tolerability for DNN applications, adaptive address remapping techniques are proposed for protecting weight data stored in flash memory. Bit significances are first analyzed to determine the priority of weight bits which should be protected. Thereafter, a novel weight transposer and an address remapper are proposed for remapping significant weight bits to fault-free or much reliable flash cells. A bipartite graph model is developed for modeling address remapping and evaluating error score. The corresponding hardware architectures for address remapping are also proposed. We use the deep learning framework pytorch for evaluating inference accuracy for different DNN models. Experimental results show that based on 0.01 % injected BER in the weight data, the accuracy losses of widely used DNN models are less than 1 % with negligible hardware overhead.

Due to the rapid technology scaling and increasing program/erase cycling, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. Conventional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER induced by increasing P/E cycles will lead to uneven distribution of errors. Applying uniform ECC protection capability for all flash pages might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash reads are required to retrieve a codeword. In this paper, ECC caching (E3C) techniques are proposed to cure these drawbacks of conventional uniform protection techniques. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. According to experimental results, we can enhance the reliability of flash memories significantly with negligible hardware cost.

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead.

Performance degradation caused by high IR-drop in normal functional mode of LSI can be avoided by improving the power supply network in the layout design phase. However, while IR-drop increases much more in test mode than in normal functional mode, excessive IR-drop in test mode is not appropriately considered in the layout design phase. Excessive IR-drop in test mode causes over-testing, which wrongly determines a fault free LSI in normal functional mode to be faulty. In this work, we propose a method for analyzing high IR-drop areas (hotspot distribution), which is necessary to effectively and efficiently reduce excessive IR-drop.

Phase change memory (PCM) is considered as the most promising alternative of DRAM. However, it has the inevitable endurance problem of the storage cells. The limited endurance and other permanent faults cause serious reliability and yield challenges. Conventional techniques like hard repair schemes and error correction codes (ECC) are usually used to overcome these dilemmas. However, since soft errors are not a main threat for PCM, equipping ECC for each data word will waste a lot of memory space for storing the check bits. Therefore, progressive ECC techniques are proposed to solve this drawback in this paper. The main idea is to equip ECC for data words when their first faulty bits are detected. That is, only the fault detection code is equipped for data words such that the original code rate is high. A separated ECC DRAM is used for storing the check bits. Two types of progressive ECC techniques¾the local progressive ECC (LPE) technique and the global progressive ECC (GPE) technique are presented. The proposed techniques are also easy to be integrated with the conventional BISR (Built-in Self-repair) architectures. According to experimental results, the degradation of repair rate and reliability are almost negligible. However, the hardware overhead is at least 70% lower than the original ECC technique.

The yield and reliability issues are important challenges for the emerging phase change memory (PCM). Hard repair techniques based on fault replacement and error correction codes are usually used to cure these dilemmas. However, the probability of occurring permanent faults is low and soft errors are not a main threat for PCM, equipping ECC for each data word will waste a lot of storage space. Therefore, an adaptive ECC technique is proposed to solve this drawback. The main idea is to equip ECC for memory words when they are detected faulty. A separated ECC DRAM is used for storing the check bits. According to experimental results, the degradation of repair rate is almost negligible. However, the hardware overhead is at least 70% lower than the original ECC technique.

We propose a supply current test method with a built-in sensor for detecting open defects on signal lines in CMOS logic circuits. The test method is based on an appearance time of dynamic supply current that flows when a test input vector is provided to a device under test. In addition, we propose a test pattern generation algorithm for the test method. An IC embedding the sensor is prototyped to examine the testability of the test method. We show by SPICE simulation and by some experiments with the IC that open defects that is undetectable by delay tests can be detected by the test method.

Based on the fault behaviors of conventional fault models, the 1-safe and 0-safe fault types are derived in this paper. We can try to store the safe value of a flash cell such that the fault effects can be masked. To boost the masking probability, both the data inversion (DI) and the page address remapping (PAR) techniques are also proposed. DI tries to complement the data bits to be programmed if their values derivate from the safe values of the corresponding faulty flash cells. PAR manipulates the logical-to-physical mapping of data words and the buffer words such that faulty cells can be programmed with their safe values. Since most of the fault effects are masked, we can reduce the strength of the adopted ECC or the amount of incorporated redundancies. The corresponding hardware architectures are also developed. A simulator is developed to evaluate the hardware overhead, repair rate, and reliability. According to experimental results, these measures can be improved significantly with negligible hardware overhead.

The distribution of data retention time of DRAM cells heavily dominates the refresh power consumption and fabrication yield. Although merely extending the single standard refresh period can effectively reduce the refresh power, however, it will incur more data retention faults (DRFs). In this paper, a novel sub-bank address remapping (SBAR) technique is proposed to cure this dilemma. Memory blocks can be refreshed adaptively based on the profile of their data retention time. SBAR uses control words for logical-to-physical address remapping such that the leakiest cells can be clustered and refreshed with their most suitable refresh periods. A refresh configuration word is used in the refresh counter for determining the length of refresh period for each memory block. For the majority of DRAM cells, they can be refreshed with a longer refresh period such that the refresh power can be effectively reduced. The corresponding hardware architecture is also proposed. Experimental results show that we can save 74.97% refresh power with less than 0.1% hardware overhead for a 1-Gb DRAM. Moreover, if there are no any repair or error correction techniques incorporated and we decrease the standard refresh period from 64 ms to 32 ms, 16 ms, or 8 ms for cells containing data retention faults, the yield can be improved 0.68, 0.96, and 1.09 times, respectively.

ECC techniques have been widely used for protecting flash memory endurance and permanent faults. Therefore, the fabrication yield and reliability can be enhanced. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC techniques, the effectiveness of the protection will decrease rapidly. In this paper, adaptive ECC techniques based on address remapping are proposed to cure this drawback. We can change the logical-to-physical address mapping of the page buffer such that faulty cells can be evenly distributed into different codewords. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the remapping algorithm and evaluating control words. Based on the control words, faulty cells can be evenly distributed into different codewords. To conduct the address remapping, a novel page buffer design is also proposed. A simulator is developed to evaluate the hardware overhead, repair rate, effective yield, and reliability. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.

In today's multi-die ICs, the die-to-die interconnects are often complicated and susceptible to various kinds of manufacturing defects and stress-induced performance degradation in the field. This phenomenon has prompted a need to perform online monitoring of the signal integrity over the die-to-die interconnects for reliability critical applications. In this work, we present a slack-time binning scheme so that one can constantly quantify the margin of a timing failure threat (TFT) occurring to a registered die-to-die interconnect. The proposed scheme attaches a Slack-Time Monitor (ST-monitor) to each Flip-Flop (FF) that receives a signal transmitted through a die-to-die interconnect under monitoring. Two techniques are introduced to enhance the traditional “Timing-Violation Checker”, namely (1) a tunable guard-band technique, and (2) an offset compensation technique. With these two techniques, one can perform online slack-time binning. Experimental results using a 90nm CMOS process show that the proposed scheme has a low area overhead of only approximately 2.35 times the area of a boundary scan cell.

Error correction code (ECC) and built-in self-repair (BISR) techniques by using redundancies have been widely used for improving the yield and reliability of embedded memories. The target faults of these two schemes are soft errors and permanent (hard) faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability, since some of the ECC protection capability is used for repairing single hard faults. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique, which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-ON test and repair stage. However, techniques are proposed to maintain the original reliability during the online test and repair stage. We also propose the corresponding hardware architecture for the EBISR scheme. A simulator is implemented to evaluate the hardware overhead (HO), repair rate, reliability, and performance penalty. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible HO and performance penalty.

Error correction code (ECC) and hard repair (built-in self-repair) techniques by using redundancies have been widely used for improving the yield and reliability of memories. The target faults of these two schemes are soft errors and permanent faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability since some of the ECC protection capability is used for repairing hard defects. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-on test and repair stage. However, techniques are proposed to maintain the original reliability during the on-line test and repair stage. We also propose the corresponding hardware architecture of the EBISR scheme. A simulator is implemented to evaluate the hardware overhead, repair rate, and reliability. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible hardware overhead.

Address scrambling and data inversion techniques are proposed for yield enhancement of NROM-based ROMs in this paper. Besides using the conventional fault replacement techniques,fault maskingeffects are also exploited to further improve the fabrication yield and reduce the amount of extra spare rows/columns. That is, we consider the logical effects of physical defects when the customer's code is to be programmed. A novel test and repair flow is also proposed. Based on the proposed techniques, possibilities of fault masking can be maximized. Arow/column scrambling control wordand acontrol columnare used for the control of the scrambling techniques and the data inversion technique, respectively. The problem for determining the control word can be modeled with a bipartite graph. The proposed test and repair techniques can be easily incorporated into the ROM BIST architectures. This makes the proposed techniques more practical to be integrated into current design flow. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead and timing penalty are almost negligible.

Fault scrambling technique is considered a promising way to distribute faulty bits into different code words such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the row/column scrambling control words. Therefore, we propose a heuristic algorithm suitable for built-in implementation for the evaluation of control words based on the fault bitmap and the specifications of the memory. The corresponding built-in scrambling analysis (BISA) circuit is also proposed. The BISA module can be easily integrated into the conventional built-in self-repair (BISR) module. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments with a prototyping IC. It is shown by the experiments that an open defect can be detected at a test speed of 1MHz.

Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection) codes will be limited. In order to cure this dilemma, efficient fault scrambling techniques are proposed in this paper. Unlike the fixed constituting memory cells of a codeword in the conventional EDAC schemes, we try to reconstruct the memory cells of code words such that each codeword consists of at most one faulty cell. The corresponding scrambling circuits are also proposed and a simulator is developed to evaluate the repair rates and hardware overhead. According to experimental results, the repair rates can be improved significantly with negligible hardware overhead.

In this paper, we propose evaluation flow for estimating the performance degradation of motion estimation (ME) architectures when faults occur and decide their acceptability. Moreover, when a fault is evaluated as unacceptable, a swap-based error-tolerance (ET) technique is proposed to increase the acceptability of this fault. According to experimental results, the acceptability and effective yield can be improved significantly with negligible hardware overhead.

Single isolated fault (SIF) stands for about 60%-70% of the total number of defects and is rather redundancy hungry since a spare row or a column is required for repairing each SIF. Therefore, manufacturing yield will decrease if we do not allocate sufficient spare resources. In this paper, instead of the traditional fault replacement techniques, synergistic techniques that integrate both fault replacement and fault masking techniques are proposed. With our approaches, SIFs are masked instead of the traditional replacement for repairing. For other minor fault types (e.g., faulty rows and faulty columns), the fault replacement technique is used as usual. According to simulation results, repair rates can be improved significantly. The proposed techniques can be integrated with the conventional built-in self-repair with nearly negligible hardware overhead.

The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in self-repair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield.

NROM is one of the emerging non-volatile-memory technologies, which provides very high data density, low fabrication cost, and better value stability. It is also promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the traditional fault replacement techniques, fault masking techniques are also exploited by considering the logical effects of physical defects when the customer's code is to be programmed. Two techniques are exploited to maximize the possibilities of fault masking-address scrambling and data inversion. Graph models are also proposed for modeling these methods. The proposed methods can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.

In this paper, efficient built-in self-repair (BISR) techniques for multiple repairable memory cores with different sizes and divided redundancy mechanisms are proposed. Embedded memory cores are first partitioned into memory groups. For each memory group, a redundant memory module is added and divided into row blocks and column blocks. Moreover, the memory cores within a memory group are partitioned into divided arrays (consisting of row/column blocks) of the same size. The redundant memory can be shared among all memory cores within the same memory group. Therefore, unlike the traditional redundancy architectures, a row (column) block is used as the basic replacement element. Based on the proposed redundancy architecture, a heuristic heterogeneous extended spare pivoting redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that the repair rate and manufacturing yield can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example memory group consisting of four memory instances of size 9.25 Mbits is only 1.12%.

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column-block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic modified essential spare pivoting (MESP) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is very low. Due to efficient usage of redundancy, the manufacturing yield, repair rate, and reliability can be improved significantly.

In this paper, BISR (built-in self-repair) techniques for heterogeneous multiple memory cores with divided redundancy mechanism are proposed. Redundant memories are partitioned into row blocks and column blocks and shared among all memory cores in the same memory group. Therefore, unlike the traditional redundancy mechanism, a row (column) block is used as the basic replacement element. Based on the proposed divided redundancy mechanism, a heuristic heterogeneous extended spare pivoting (HESP) redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that repair rates can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example with four memory instances is only 1.12%.

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic MESP (modified essential spare pivoting) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is almost negligible. Due to the efficient usage of the redundancy, the manufacturing yield, repair rate, and reliability can all be improved significantly.

Owing to the rapid advance in semiconductor fabrication technology, a large number of transistors can be incorporated onto a single chip. However, this will reduce the controllability and observability of the chip significantly. Consequently, testing such highly complex and dense circuits becomes very difficult and expensive. Therefore, we propose an efficient design-for-testability technique based on M-testability conditions for the 2D systolic DCT/IDCT processors in this paper. The cell fault model is adopted. For chip testing consideration, we modify the processing elements of the 2D array and make the module function bijective. The proposed DFT technique is also suitable for BIST implementation. The test pattern generator is simply a binary counter. Moreover, the adders and registers in each processing element can be combined as signature analyzers to perform accumulation and compression operations to evaluate the signatures during different test sessions. The signatures for each test session are stored in each processing element and propagated to the primary outputs when the test session is finished. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture for 2D DCT/IDCT architectures is less than 10%. The fault coverage of each processing element can achieve 98.18%

As the complexity and size of the embedded memories keep increasing, improving the yield of embedded memories is the key step toward improving the overall chip yield of a SOC design. The most well known way to improve the memory yield is by using redundant elements to replace the faulty cells. However, the repair efficiency mainly depends on the type, and the amount of redundancy; and on the redundancy analysis algorithms. Therefore, new types of redundancy based on divided bit-line (DBL), and divided word-line (DWL) techniques are proposed in this work. A memory column (row), including the redundant column (row), is partitioned into column blocks (row blocks), respectively. A row/column block is used as the basic replacement element instead of a row/column for the traditional approaches. Based on the new types of redundancy, three types of fault-tolerant memory (FTM) systems are also proposed. If a redundant row/column block is used as the basic replacement element, then the row block-based FTM (RBFTM)/column block-based (CBFTM) system is used. If both the DWL, and DBL techniques are implemented onto a memory chip, then the hybrid FTM (HFTM) system is achieved. The storage and remapping of faulty addresses can be implemented with a CAM (content addressable memory) block. To achieving better repair efficiency, a novel hybrid block-repair (HBR) algorithm is also proposed. This algorithm is suitable for hardware implementation with negligible overhead. For the HFTM system, the hardware overheads are less than 0.65%, and 0.7% for 64-Kbit SRAM, and 8-Mbit DRAM, respectively. Moreover, the repair rate can be improved significantly. Experimental results show that our approaches can improve the memory fabrication yield significantly. The characteristics of low power and fast access time of DBL and DWL techniques are also preserved.

A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024/spl times/2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.

As checking spam became part of our daily life, unsolicited bulk e-mails (UBE) have become unmanageable and intolerable. Bulk volume of spam e-mails delivering to mail transfer agents (MTAs) is similar to the effect of denial of services (DDoS) attacks as it dramatically reduces the dependability and efficiency of networking systems and e-mail servers. Spam mails may also be used to carry viruses and worms which could significantly affect the availability of computer systems and networks. There have been many solutions proposed to filter spam in the past. Unfortunately there is no silver bullet to deter spammers and eliminate spam mails. That is, in isolation, each of existing spam protection mechanisms has its own advantages and disadvantages. In this paper, we analyze the shortcomings of existing anti-spam solutions and propose a multi-faceted approach using the spam-resistible mail agent (SRMA), which provides the most advantages and the least disadvantages of existing anti-spam solutions. Our experiments show that the proposed SRMA is immune to existing spambots and the prototype proves to be effective, feasible and deployable.

In this paper, we first propose a novel design-for-testability approach based on M-testability conditions for module-level systolic fast Fourier transform (FFT) arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, fault-tolerant approaches at the bit level and the multiply-subtract-add (MSA) module level are proposed, respectively. If the reconfiguration is performed at the bit level, then the FFT/sub BIT/ network is constructed. Two types of reconfiguration schemes (Type-I FFT/sub MSA/ and Type-II FFT/sub MSA/) are proposed at the MSA module level. Since both the design for testability (DFT) and the design for yield (DFY) issues are considered at the same time for all these proposed approaches, the resulting architectures are simpler as compared with previous works. The reliability of the FFT system increases significantly. The hardware overhead is low-about 12% and 1/2N for the FFT/sub BIT/ network and the Type-II FFT/sub MSA/ network, respectively. An experimental chip is also implemented to verify our approaches. Reliabilities and hardware overhead are also evaluated and compared with previous works.

In this paper, a ping-pong type fault detection and fault diagnosis technique for field programmable gate arrays (FPGAs) is proposed. Efficient (k + 1) test configurations for a single configurable logic block (CLB) are first derived and proved that 100 % fault coverage can be obtained, k denotes the number of inputs of an LUT. Thereafter, the whole CLB array is divided into cell groups and each group contains 2 cells-the master cell and the slave cell. Since both cells can be used as the test pattern generator (TPG) and the block under test (BUT) at the same time, one test session is required instead of two test sessions for traditional fault detection techniques. Therefore, the test complexity is reduced significantly. Multiple fault detection and location can be easily achieved. Since the number of test sessions is less than the traditional approaches, significant speedup can be obtained. Comparisons with other works based on detection and diagnosis complexity are also given.

Efficient built-in self-test techniques for memory-based FFT processors are proposed. The memory-based architecture is suitable for high computation point applications such as ADSL and OFDM systems. The FFT processor is first divided into the memory part and the logic part which can be tested under the supervision of the same BIST controller. The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part. The adopted memory test algorithm can be programmed by the users which covers different types of memory faults. For the logic part, the single cell fault model is assumed. Our BIST architecture tests both parts simultaneously such that the test time can be reduced greatly. The hardware overhead of our approach is also very low since novel design-for-testability techniques are applied for the logic part which mainly consists of multipliers. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture is only 4.06%. The fault coverage of the memory part depends on the March algorithm adopted. For the logic part, we can achieve 100% cell fault coverage with only 16 test patterns.

In this paper, we present a novel fault detection and fault diagnosis technique for field programmable gate arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. The input patterns can be easily generated with a k-bit binary counter. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. To locate a faulty CLB (configurable logic block), two diagnosis sessions are required. However, the maximum number of configurations is k+4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable with our approach.

In this paper, we first propose a testable design scheme for FFT butterfly networks based on M-testability conditions. Based on them, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, a reconfiguration mechanism is used to bypass the faulty cell and the testable/fault-tolerant FFT networks are constructed. Special cell designs are presented which implement the reconfiguration mechanism. The reliability of the FFT system increases significantly. The chip design for the bit-level butterfly module is presented. The hardware overhead is low - about 12% for the bit-level design. For the module-level design, it leads to a lower hardware overhead (about 1/2N, where N is the computation point).

Iterative logic arrays are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. Therefore, in order to improve the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as the sequential fault models and the delay fault models should also be considered. Therefore, delay fault testability conditions are proposed for iterative logic arrays (ILAs) in this paper. Our approach applies to ILAs with an arbitrary dimension, e.g., linear and mesh-connected ILAs, etc. Moreover, it can also be applied to various other connection types, e.g., butterfly-connected and shuffle-connected ones. A design for-testability approach is used to make these arrays delay fault testable based on the proposed testability conditions. To illustrate our approach, we give a delay fault testable FFT processor as an example and show that an overhead of no more than 5% is sufficient to make it C-testable. It requires only 128 2-pattern tests to achieve 100% cell-delay-fault coverage regardless of the word length and the computation points of the FFT processor. Our approaches also guarantee that the test set is easy to generate, and the corresponding BIST structure requires smaller hardware overhead and has a more regular structure.

An efficient approach to determining the reliability of an undirected k-terminal network based on 2-terminal reliability functions is presented. First, a feasible set of (k-1) terminal-pairs is chosen, and the 2-terminal reliability functions of the (k-1) terminal-pairs are generated based on the edge expansion diagram using an OBDD (ordered binary decision diagram). Then the k-terminal reliability function can be efficiently constructed by combining these (k-1) reliability expressions with the Boolean and operation. Because building 2-terminal reliability functions and reducing redundant computations by merging reliability functions can be done very efficiently, the proposed approaches are much faster than those which directly expand the entire network or directly factor the k-terminal networks. The effectiveness of this approach is demonstrated by performing experiments on several large benchmark networks. An example of appreciable improvement is that the evaluation of the reliability of a source-terminal 3/spl times/10 all-terminal network took only 2.4 seconds on a SPARC 20 workstation. This is much faster than previous factoring-algorithms.

In the area of high capacity RAMs, the memory columns (rows), including the redundancies, are partitioned into column blocks (row blocks), respectively. If the replacement is performed at the row-block level, then a row block-based FTM (RBFTM) system is used. Alternatively, if the replacement is performed at the column-block level, then a column block-based FTM (CBFTM) system is used. If both approaches are incorporated into a memory chip, then the hybrid FTM (HFTM) system is achieved. Experimental results and analysis show that our fault-tolerant architectures can improve the yield for memory fabrication significantly. The reconfiguration mechanism requires almost negligible hardware overhead for high capacity memories. Moreover, the repair rates among different fault-tolerant strategies are also compared.

With the advent of VLSI technology, a large collection of processing elements can be gathered to achieve high-speed computation economically. However, due to the low pin-count-to-component-count ratio, the controllability and observability of such circuits decrease significantly. As a result, the testing of such highly complex and dense circuits becomes very difficult and expensive. A testable/fault-tolerant FFT processor is proposed in this paper. We first propose a testable design scheme for FFT butterfly networks based on M-testability conditions. According to the M-testability conditions, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, a reconfiguration mechanism is incorporated to bypass the faulty cells and the testable/fault-tolerant structures are constructed. Special cell designs are presented to implement the design-for-testability and reconfiguration mechanisms. The reliability of the FFT system increases significantly and the hardware overhead is low-about 16% for the module-level design.

A novel built-in self-test structure for the lookup table (LUT) based field programmable gate arrays (FPGA's) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLB's) is assumed. The whole chip is partitioned into disjoint one-dimensional arrays of cells. We assume that in each linear array, there is at most one faulty cell, and a faulty cell may contain multiple faulty CLB's. Our idea is to configure the cells to make each cell function bijective. In order to detect all faults defined, k+2 configurations are required. The input patterns can be easily generated with a k-bit counter and the fault coverage is 100%. The number of configurations for our BIST structures is 2k+4. Our BIST approaches also have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three test sessions are required. However, the maximum number of configurations is k+4 for diagnosing a faulty CLB.

Continuous progress in VLSI technologies keeps reducing the defect density. However; a yield of 100% is considered unlikely. It is also known that VLSI circuits can never be "completely" tested. Therefore, defect level cannot be reduced to zero. The quality of a test is usually evaluated by the fault coverage. The relationship between the defect level and the fault coverage has never been proposed. In this paper; we first propose the concept of multi-model fault coverage (MFC) instead of the fault coverage based on a unique fault model. The relationship between defect level, fabrication yield, and multi-model fault coverage is then derived. We also analyze the defect level error between the predicted defect level and the physical defect level. As the number of fault models used increases, the defect level error can be reduced significantly. Our approach is very effective for product quality prediction and the concept of multi-model fault coverage is very useful for today's system-on-chip technology.

Highly reliable interleaved memory systems for uniprocessor and multiprocessor computer architectures are presented. The memory systems are divided into groups. Each group consists of several banks and each bank has several modules. The error model is defined at the memory-module level. A module is faulty if any single or multiple faults result in loss of the entire module. Spare modules, as well as spare banks, are included in the systems to enhance reliability and availability. A faulty module is replaced by a spare module within a bank first, and, if the bank has no redundancy remaining for the faulty module, the whole bank will be replaced by a spare bank at the next higher level. The structure of the reconfigurable memory system is designed in such a way that the replacement of faulty modules (banks) by spare modules (banks) will not disturb memory references if each bank (group) has at most two spare modules (banks). If there are more than two spare modules (banks) in a bank (group), a second-level address translator is designed which can prohibit references to faulty modules by address remapping. The address translator can be implemented with a CAM or switches. Analysis results show that the system reliability can be significantly improved with little hardware overhead. Also, a typical system with one redundant row of modules has the highest cost-effectiveness during its useful lifetime period. User transparency in memory access is retained.

A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table augmentation approach. We propose an output-assignment algorithm for minimizing the hardware overhead. We give a CMOS systolic array multiplier as an example, and show that an overhead of no more than 5.88% is sufficient to make it C-testable, i.e., 100% single cell-fault testable with only 18 test patterns regardless of the word length of the multiplier. Our technique guarantees that the test set is easy to generate. Its corresponding built-in-self-test structures are also very simple.>

Design-for-testability techniques and built-in self-test structures are presented for cellular arrays based on the M-testability condition, which results in the minimal number of tests. This technique applies to arrays with arbitrary dimensions and various connections. A systolic array multiplier is given as an example, showing an overhead of only 4% for making it M-testable. This method compares favorably with that based on pI-testability. It reduces drastically the testing costs for circuits realized as cellular arrays.>