The problem of adding k n-bit numbers, where k ≥ 3 is considered. A novel scheme for adding such k numbers is described. Applying the bit-partitioning technique so that each partition contains m bits of each of these k numbers, where m=[log2(k-1)] is an integer ≥ log2(k-1), the final sum can be obtained in m+1 addition cycles.

This paper presents an alternate approach to the problem of delayed-input circuit realization of any fundamental mode asynchronous flow table. This approach is based on partition theory. It is shown that an equivalent normal primitive flow table of any reduced flow table has n binary partitions with substitutioh property such that their product is a 2nblock partition with substitution property, where n is the number of binary inputs. Such a property leads directly to a circuit which realizes the flow table and is a serial connection of two smaller subcircuits. The first subcircuit is again decomposable into n smaller circuits connected in parallel. It is shown that these n circuits always correspond to trivial delays in the input lines, thus leading to the delayed-input circuit realization of the fundamental mode flow table.

This paper considers the problem of designing an n-input, n-output, asynchronous unit delay (AUD) [2], [7], [13]. In the general case, all input changes are allowed in an AUD. However, the restricted case where only single input changes are allowed has been investigated in detail. Starting with linear single error-correcting codes, an unusual method of obtaining a uniquely reduced flow table of a restricted AUD is developed. Such a reduced table has 2k substitution property (SP) partitions [15] on the set of internal states whose product is the zero partition, where k is the smallest integer equal to or greater than log2 n. Hence, the state behavior of an n-input n-output restricted AUD is realizable by 2k two-state sequential circuits connected in parallel [15]. A direct algorithm for obtaining this realization is also given.

An "asynchronous unit delay" is an n-input n-output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of input n-tuple prior to the last input change. In this paper it is shown that such a circuit can be used as a basic building block in the design of any asynchronous circuit. It is shown that any fundamental mode flow table is realizable by a circuit of feedback index m with one asynchronous unit delay, m inertial delays, and a combinational network, where m is the smallest integer ≥ {log2 max (Si)} and Si is the number of stable states in any input column of the table. A straightforward method of realizing "asynchronous indefinite" fundamental mode tables without critical races by circuits of feedback index 1 with k asynchronous unit delays, one inertial delay, and combinational gates is also suggested. The approach suggested in this paper avoids complicated secondary assignment problems, results in circuits with simple structure, and further, brings closer the theories of synchronous and asynchronous sequential circuits.

An asynchronous unit delay is an n input n output asynchronous sequential circuit in which the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining when a fundamental mode flow table is realizable as a feedback-free connection of asynchronous unit delays. It is shown that such a realization exists if and only if the flow table is asynchronous definite, where the asynchronous definite property is a modification of the definite property of synchronous sequential machines. A straightforward method of realizing asynchronous definite flow tables without critical races by feedback-free circuits of asynchronous unit delays and combinational gates is developed. The use of asynchronous unit delays for definite tables avoids complicated secondary assignment problems, results in circuits with very simple structure, and brings closer the theories of synchronous and asynchronous sequential machines.