This paper presents a hybrid step-up converter with only one inductor and one flying capacitor. The proposed converter features a left-half-plane zero rather than a right-half-plane one. With a broad bandwidth up to a tenth of the switching frequency, the converter can attain a fast transient response as a buck converter. In addition, the voltage conversion ratio of the proposed converter is identical to that of the conventional boost converter, thereby enabling a wide range of output voltage in systems powered by lithium-ion batteries. Measurement results demonstrate that a peak efficiency of 95.1% is obtained. Given a load current stepping from 50 mA to 500 mA in less than 160 ns, the settling time is merely $2.8 \mu \mathrm{~s}$.

This paper proposes a novel noise-shaping (NS) successive approximation register (SAR) based light-to-digital converter (LDC) for continuous multi-wavelength (MW) photoplethysmogram (PPG) monitoring. The proposed NS-SAR LDC employs a single-channel current-integration (CI) SAR quantizer with a three-channel passive NS loop filter performs time-multiplexed, low-power NS readout for MWPPG. The cascade integrator feedforward NS architecture features a passive nested feedback path, which contributes one additional NS order. The LDC enables a wide dynamic range (DR) through the high signal-to-noise-and-distortion ratio (SNDR), inherent AC gain control of the proposed CI NS-SAR, and a predictive threshold filter that compensates for large DC and drifting baseline currents induced by motion artifacts and interference light. Fabricated in a 180-nm standard CMOS process, the NS-SAR LDC consumes$26.5~\mu $W while achieving a SNDR of 95 dB and a total DR of 161.5 dB. The work is validated through finger MWPPG measurements using commercial PPG sensors.

This article presents a dual-phase hybrid dc—dc converter (DPHC) for the applications of high voltage conversion ratio and high output current delivery. The power stage topology evolved from the tri-state double step-down (DSD) topology by inserting a single additional power switch and a flying capacitor. Unlike conventional multi-phase converters that require equal inductor current sharing among all phases, the proposed converter allows intentionally unequal current distribution, which reduces current stress on specific components and improves overall efficiency. Additionally, all the flying capacitor voltages ($V_{{CF}}$) of the proposed DPHC are self-balanced during steady-state operation, cutting down the requirement for the circuit design for$V_{CF}$calibration. The proposed DPHC retains the characteristics of some other existing multi-level multi-phase hybrid topologies with fewer components. A PCB prototype is built to verify the performance of the proposed DPHC. Experimental results show that the peak efficiencies of the proposed DPHC are 94.6% and 91.1% respectively for the voltage conversion of 24 V/48 V to 1 V.

This paper presents a hybrid boost converter with a feature of “always’ reduced inductor current, enabling the usage of a low-profile inductor with high dc resistance (DCR) without compromising the power efficiency. The proposed boost converter also features a wide range of voltage conversion ratios as the conventional boost converter (CBC). Additionally, the output current of the proposed boost converter can be delivered continuously, and thus the output voltage ripple magnitude is reduced. Detailed dc analysis and small-signal modeling of the proposed converter are also included in this paper. Simulation results show that the average inductor current of the proposed boost converter can be greatly reduced compared with the CBC. The peak efficiency of 96.3% is achieved when an inductor with DCR of 250 mΩ is used.

This work presents a low-power, large cross-scale dynamic range (DR) successive approximation register (SAR) based light-to-digital converter (LDC) designed for wearable multi-wavelength photoplethysmogram (MWPPG) readout. The proposed SAR-LDC employs a current-integration SAR (CI-SAR) quantizer that directly integrates the photocurrent onto a binary capacitive digital-to-analog converter (DAC) and utilizes low-power SAR logic for direct digitization. This approach releases the various trade-offs present in the recent LDC designs and further maximizes the LDC’s power efficiency. At the circuit level, an AC/DC correlated DR enhancement loop, controlled by a digital reconfigurable unit (DRU), enhances both the DC and AC DR of the proposed system. The proposed architecture is fabricated in standard 180-nm CMOS technology. By utilizing a 10-bit SAR-LDC, it achieves a maximum effective number of bits (ENOB) of 9.93 and 12.56 in the Nyquist bandwidth and PPG bandwidth, respectively. The SAR-LDC reads MWPPG on a single channel through time multiplexing, consuming 9.84 μW only while achieving a cross-scale AC DR of 103.4 dB and a total DR of 148.9 dB without using any hybrid circuit technique. The proposed SAR-LDC is further validated using with a commercial PPG sensor for finger MWPPG measurement.

This brief presents an adaptive zero-current detector (ZCD) for the single-inductor multiple-output (SIMO) DC-DC converter with a full-wave current sensor. The innovative adaptive ZCD, which can be applied to the order power distribution control (OPDC) SIMO DC-DC converter, is designed, and it can accurately turn off the low-side power switch when the SIMO DC-DC converter operates in the discontinuous conduction mode. Besides, a new full-wave current sensor which contains only one sensing transistor is presented, and it can precisely sense the inductor current with a small delay. The SIMO DC-DC converter is designed and fabricated in a standard 65 nm CMOS process with output power ranges from 3.7 to 925 mW. The measured reverse current is reduced by up to 78.2%, and the measured light-load power efficiency is improved by up to 10%.

In high power application, a single active power filter (APF) limited by its capacity cannot compensate for whole harmonics. APF parallel system is thus adopted to solve this problem. Centralized control scheme for the parallel system features good current sharing ability, but subject to communication fault. On the other hand, decentralized control schemes cannot share current properly. This paper proposes a decentralized control scheme for modular APF parallel system in which all APF modules have equal status and share the current in proportion to their own capacities without central controller. What is more, plug and play of an APF is achieved, and current sharing can be done automatically. The correctness and effectiveness of the scheme have been testified by simulations.

This paper presents a fast-response output-capacitorless low-dropout regulator (OCL-LDO) using a high slew-rate input stage and improved multipath nested Miller compensation (MNMC). With the specially-designed input stage, the quality factor (Q) of the transfer loop is greatly reduced. The circuit is implemented in a standard 65-nm CMOS process. The total on-chip compensation capacitance is 0.5 pF only. The designed OCL-LDO regulator features over 150 MHz unity-gain bandwidth (UGB) at zero load and keeps UGB higher than 100 MHz up to 45 mA loading. For the maximum 60-mA load transient with 10-ns edge time, the voltage spikes are controlled around 20 mV.

A two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain- bandwidth product (GBW). Implemented in a standard 0.13-μm CMOS technology and powered by a 0.7 V supply with a current consumption of 20 μA, the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/μs. The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.

A gain and slew rate enhancement technique for amplifiers, based on starving current in static state and feeding excessive current during slewing, is proposed in this paper. Demonstrated in a current-mirror amplifier using a standard 0.18-μm CMOS process, the dc gain is boosted by 15 dB, and the slew rate is enhanced by over 600% compared with a conventional current mirror amplifier and 1100% compared with a current-starved amplifier. In the meanwhile, static power consumption is reduced by more than 2/3 without sacrificing unity-gain frequency, output swing or stability. The total power dissipation is only 63.4 μW under 1.8 V supply.

A modified structure of OTA in CMOS 65-nm with signal- and transient-current boosting is presented in this paper. The structure uses simple cascode current mirrors to overcome channel-modulation effect of the 65-nm MOSFETs and to maintain low-error current matching. Simulations show that the parasitic poles of the OTA in CMOS 65-nm are located at very high frequencies and the achievable bandwidth is much increased with sufficient phase margin to maintain closed-loop stability.

This paper presents a fixed-frequency auto-buck-boost SIMO dc-dc converter with duty-cycle redistribution and duty-predicted current control. The switching sequence of the power transistors in the power stage and the controller design achieve fixed-frequency operation with an optimized duty-cycle allocation, to deal with static and dynamic unbalanced loading conditions of different channels. The proposed control scheme reduces average inductor current for reducing conduction loss and cross regulation during load transients.

This paper presents a low power, long-transmission distance, high data rate intrabody communication (IBC) analog receiver front end (RFE). First, to optimize the transmission performance, conventional transmission line analysis scheme is creatively adopted to the IBC design to characterize the body channel. Second, switched-capacitor filters based on sampling rate boosting technique are adopted for higher accuracy and lower power consumption. Third, a novel RFE topology is proposed to further enhance the IBC performance. The new RFE is designed and fabricated in a standard 180-nm CMOS process. Measurement results show that the RFE can successfully transmit data spanning the whole human body, around 180 cm, which is one of the longest transmission distances reported in related literatures. Furthermore, it reaches a maximum data rate of 2.5 Mb/s with a bit error rate less than 1e-7 and consumes 5.4 mW from a 1.8 V supply. The proposed RFE compares favorably to similar reported works.

This paper presents a sub-mW, current-reused first-harmonicLCinjection-locked oscillator (ILO) using in-phase dual-input injection technique. It can be used as a power oscillator in the injection-locked transmitter of wireless biomedical sensor nodes (WBSNs) integrated into a wireless body area network. A prototype chip, implemented in a standard 0.13-μm CMOS process occupying 200 × 380 μm, operates in the medical implantable communications service (MICS) band for medical implants. Measurement results show that the proposed ILO features a wide locking range of 800 MHz (150-950 MHz) at an input power of 0 dBm. More importantly, it has a high input sensitivity of -30 dBm to lock the 3-MHz bandwidth of the MICS band, while consuming only 660 μW at 1-V supply. This ultralow power consumption enables autonomous WBSNs.

Hysteresis voltage-mode control is a simple and fast control scheme for switched-mode power converters. However, it is well-known that the switching frequency of a switched-mode power converter with hysteresis control depends on many factors such as loading current and delay of the controller which vary from time to time. It results in a wide noise spectrum and leads to difficulty in shielding electro-magnetic interference. In this work, a phase-lock loop (PLL) is utilized to control the hysteresis level of the comparator used in the controller, while not interfering with the intrinsic behavior of the hysteresis controller. Some design techniques are used to solve the integration problem and to improve the settling speed of the PLL. Moreover, different control modes are implemented. A buck converter with proposed control scheme is fabricated using a commercial 0.35-μ m CMOS technology. The chip area is 1900 μm × 2200 μm. The switching frequency is locked to 1 MHz, and the measured frequency deviation is within ±1%. The measured load transient response between 160 and 360 mA is 5 μ s only.

This paper presents three different topologies of energy-efficient fast-transient low-dropout regulators (LDOs) for SoC applications. They include: 1) an output-capacitorless LDO with a direct voltage-spike detection circuit, 2) an output-capacitorless 90-nm LDO compensated by a single Miller capacitor, and 3) a power-efficient 90-nm LDO with multiple small gain stages. The LDO designs demonstrate some recently developed circuit techniques to improve both the regulation accuracy and transient performance. Experimental results are included in this paper to verify the achieved performance.

This paper presents an error amplifier structure to improve load regulation of low-voltage low-dropout regulators. The proposed error amplifier has ultrawide swing to extend the high-gain region so that the size of power transistor can be reduced. Experimental results show that the required power transistor size is reduced by 25% to achieve similar performance in load regulation. Moreover, extra power consumption and increase of silicon area are not significant.

In this paper, a low-power signal processing front-end and PIE decoder for use in UHF RFID passive transponders is presented. By merging with the decoder, the clock generator does not need to drive a large loading capacitor. Therefore, its power consumption can be greatly reduced. In addition, the ring oscillator of the generator was designed for low sensitivity to supply voltage variation and low power consumption. Fabricated in a 0.13-mum CMOS process, the measured power consumption consumes only 850 nW.

Multiband orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) systems have drawn much attention for its high spectrum efficiency and multiple access capability. However, its large throughput requirement and low power spectral density result in high hardware complexity and high power consumption, which are challenges of designing the packet detector. In this paper, a novel detection method is proposed with very good detection performance in low SNR. Low cost and low power schemes are also introduced in circuit design to save 70% area and 71% power. The proposed packet detector is synthesized with UMC 0.13 mum library at 132 MHz clock frequency. The hardware cost is 56.9 K gates and the power consumption is only 11.7 mW.

A fold-back current-limit circuit, with load-insensitive quiescent current characteristic for CMOS low dropout regulator (LDO), is proposed in this paper. This method has been designed in 0.35 mum CMOS technology and verified by Hspice simulation. The quiescent current of the LDO is 5.7 mA at 100-mA load condition. It is only 2.2% more than it in no-load condition, 5.58 mA. The maximum current limit is set to be 197 mA, and the short-current limit is 77 mA. Thus, the power consumption can be saved up to 61% at the short-circuit condition, which also decreases the risk of damaging the power transistor. Moreover, the thermal protection can be simplified and the LDO will be more reliable.

The proposed single-inductor dual-output (SIDO) buck-boost DC-DC converter operating in pseudo-DCM/CCM mode can adaptively increase the pseudo DC inductor current to improve the transient load response and the load driving capability in terms of the load change. A maximum duty cycle limiter is used to remove cross regulation and determine the compensation current on the set pseudo DC current. A buck sub-converter and a boost sub-converter are combined with an optimized number of switches. Based on the operating mode and an integrated error amplifier design, the off-chip compensation network is removed. In addition, the transfer functions of the power stage of SIDO DC-DC converter operating in the pseudo-DCM/CCM mode is also presented.

This paper introduces an alternative structure to implement damping-factor-control frequency compensation for three-stage amplifiers. A theoretical analysis is presented, and experimental results are included. From the experimental results, the new structure provides better phase margin and power supply rejection ratio but higher power consumption and larger chip area are required.