Recently, multithreading became a standard technique to improve the processor utilization and system performance. Hardware support is provided for coarse-grained as well as simultaneous multithreading. In particular, embedded devices combine processor cores and varying sets of coprocessors to fulfill the requirements of their dedicated application field. In this paper, a simultaneous multithreaded processor is investigated that applies dynamic priorities for each thread on the instruction level. By means of a synchronization coprocessor, priorities of threads are dynamically adapted when other threads have to wait for a given thread. Based on simulations of a network-processing workload, two strategies of dynamic priority adaptation are evaluated and compared with static prioritization. As a result, performance gain can be shown.

Robust Header Compression (ROHC) provides for more efficient use of radio links for wireless communication in a packet switched network. Due to its potential advantages in the wireless access area and the proliferation of network processors in access infrastructure, there exists a need to understand the resource requirements and architectural implications of implementing ROHC in this environment. We present an analysis of the primary functional blocks of ROHC and extract the architectural implications on next-generation network processor design for wireless access. The discussion focuses on memory space and bandwidth dimensioning as well as processing resource budgets. We conclude with an examination of resource consumption and potential performance gains achievable by offloading computationally intensive ROHC functions to application specific hardware assists. We explore the design tradeoffs for hardware assists in the form of reconfigurable hardware, Application-Specific Instruction-set Processors (ASIPs), and Application-Specific Integrated Circuits (ASICs).