Demo Data from VLDB 2026 / reviewers in the wild / expert
Stefano Di Francescantonio
dblp:62/6137
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 93% Processor architecture and microarchitecture · 7% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault modeling |
0.0 | 1 | 2004 | Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing · IEEE Trans. Computers 2004 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2004 | Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing · IEEE Trans. Computers 2004 |
Electronic design automation › hardware test › integrated circuit testing
inductive fault analysis |
0.0 | 1 | 2004 | Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing · IEEE Trans. Computers 2004 |
Electronic design automation › hardware verification and test › VLSI testing
manufacturing test |
0.0 | 1 | 2004 | Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing · IEEE Trans. Computers 2004 |
Methods — techniques the papers use, named apart from their topics
inductive fault analysis · 0.0electrical-level simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing TestingabstractBased on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most likely to affect signals of the clock distribution network. Their probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations. We have found that, contrary to common assumptions, only a small percentage of such faults result in catastrophic failures easily detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself. Cecilia Metra, Stefano Di Francescantonio |
IEEE Trans. Computers | 2 |
| 2002 | Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line TestingabstractThis paper investigates the impact of faults affecting the clock distribution network of synchronous systems on manufacturing testing. Previous researches based on real process data and inductive fault analysis of a reference microprocessor showed that, contrary to common expectations, the majority of clock faults leads to local failures not likely to be detected by manufacturing testing, despite their ability to compromise the microprocessor operation and reliability. This paper shows that clock faults can be detected by means of conventional stuck-at, delay and transition testing in only 12% of cases and that in 10% of cases the undetected clock faults invalidate the testing procedures themselves. In addition, in the 29% of cases, clock faults are likely to cause race conditions that, although generally not considered by delay fault testing, might as well compromise system's correct operation. The possible adoption of on-line testing techniques to avoid such dangerous conditions is finally discussed. Cecilia Metra, Stefano Di Francescantonio |
ITC | 2 |
| 2002 | On-Chip Clock Faults' Detector
Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò |
J. Electron. Test. | 3 |