This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.

This article presents a four-phase adaptive on-time (AOT) controlled buck converter with an ultra-fast load-transient response. A dynamic-frequency clock generator is proposed to generate and auto-synchronize three duty signals with 90°, 180°, and 270° phase shifts based on an already-generated duty signal. Interleaving angles between phases are always kept constant even when the switching frequency varies. Unlike the traditional pulse distribution scheme in constant on-time (COT) multiphase buck converters, the generated pulses no longer need to be sequentially distributed to different phases, but synchronized to one phase instead. Therefore, a much faster load-transient response can be achieved. A transient-enhancement scheme is also proposed to remove the speed limitations introduced by the error amplifier (EA) during load transient. The fast response merits of the AOT controller can thereby be fully taken advantage of while a relatively constant operating frequency is maintained under different input and load conditions. Simulated in a 180-nm BCD process, the proposed converter shows a fast load-transient response with 102-mV output voltage droop and 754-ns settling time for a 6A/1ns rapid load current step, where a 22-μF decoupling capacitor with a relatively large equivalent series resistance (ESR) of 15 mΩ is used. Besides, this work achieves a peak efficiency of 89.7% for 5V-to-1.4V conversion, while the efficiency is maintained at >75% over a wide load range from 1 A to 10 A.

Conventional noise-shaping (NS) SAR ADCs require a high-quality power supply provided by the power management system consisting of a DC-DC converter and a low dropout (LDO) regulator. However, the LDO’s dropout voltage limits the power system’s efficiency. To enhance efficiency, this paper proposes removing the LDO. Nevertheless, the voltage ripple generated by the DC-DC converter will directly inject into the ADC, causing two issues: 1) ripple modulation with signal, generates modulation tones that affect the linearity, and 2) ripple modulation with shaped-quantization-noise, folding into baseband and increasing in-band noise. To mitigate these errors, we propose a proper frequency management scheme based on oversampling and a low-pass filter (LPF) integrated into the noise transfer function (NTF) of the NS-SAR. This paper implements a 2-channel time-interleaved (TI) NS-SAR ADC with 2nd-order NS and 2nd-order LPF. The prototype, fabricated in a 28nm CMOS process, operates with 1V provided by a boost DC-DC converter with 0.55V input. It achieves an 80-dB-SNDR over a 3-MHz-BW, operating at a sampling rate of 330MS/s with the DC-DC converter switching frequency of 145MHz. The total system consumes 3.59mW, with the ADC itself consuming 3.02mW, and exhibits a Schreier FoM (FoMS) of 170 dB. By removing LDO, the total system efficiency reaches 84.1%.

This work presents a high energy-efficiency mixed-signal multiply-and-accumulate (MAC) macro in charge-domain for machine learning (ML) systems. It involves crucial features aimed at enhancing energy efficiency, throughput, and area efficiency, namely: 1) a parallel-serial (ParSer) scheme to augment the throughput by parallel input channels and reduce the power via serial analog accumulation rather than digital summation; 2) the weight-independent parallel digital-to-analog converter (DAC) sampling (WIPDS) to cancel weight nonlinearity during sampling and allow for resource-efficient DAC, significantly saving power and area; 3) a high energy-efficiency dynamic amplifier (DA) introduced to improve drivability and counteract attenuation of the serial accumulation, thereby attaining the desired accuracy with relaxed the afterward analog-to-digital converter (ADC) resolution and consequently reducing power consumption; 4) an optimized SAR ADC to reach higher energy efficiency. Fabricated in 28-nm CMOS technology, the prototype exhibits a peak energy and area efficiency of 362 TOPS/W and 3.23 TOPS/mm$^{2}$, respectively.

Gallium-Nitride (GaN) high electronic mobility transistor (HEMT) enables faster switching frequency for buck converters. Therefore, high dV/dt immunity and small deadtime of the switching node become important indicators for GaN-based buck converter. This paper presents a high switching frequency GaN gate driver with an asymmetrical noise current clamping technique for the floating level shifter for 5000V/ns dV/dt noise immunity in simulation and over 60V/ns immunity in measurement. Meanwhile, the proposed deadtime generator achieves adaptive deadtime control without a down level shifter nor fast comparator for sensing operation state of the buck. The proposed driver was implemented in a$0.18\mu $m BCD process, used in a GaN-based buck converter for verification. It achieves 7.45ns and 1.1ns deadtime for the VSWtrailing and leading edge, respectively. The buck converter obtains 86.5% peak efficiency for 12V-5V conversion, with 10MHz switching frequency.

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.

Smart meter monitors electricity consumption through modern metering devices connected to the Internet via Internet of Things (IoT) technology, which can provide intelligent and fast applications on-site such as arc fault protection based on nonintrusive monitoring load classification with fast safety responses for varying electric loads. Traditional three, four, and five layers of the IoT architecture cannot support such fast responses under loading variation. This article aims to propose six layers of IoT Cloud-Edge Infrastructure equipped with a reconfigurable mixed-signal controller as a smart meter platform for adaptation to different environments and, for example, deal with fast arc fault detection corresponding to different load characteristics. Such an architecture can reduce the processing time for safety, reduce bandwidth for communication, improve arc detection accuracy under different loading environments, and lower the overall computation cost.

This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to overcome the SAR ADC’s speed bottleneck. Benefiting from this technique, the sampling rate of the prototype 10b single channel 1b/cycle SAR ADC reaches 600 and 700 MS/s at 0.9 and 0.95 V supply voltage, while consuming 1.49 and 2.02 mW in 28 nm CMOS, respectively. Moreover, the 10b ADC achieves the SNDR of 56.39 and 56.42-dB at a Nyquist rate input frequency of 600 and 700 MS/s, leading to a Walden FoM of 4.6 and 5.3 fJ/conversion-step, respectively.

This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order delta-sigma modulator (DSM). It uses the information from one complete channel to predict the other channel based on the extrapolation principle. Note that, Cascaded Integrator of Distributed Feedforward (CIFF) topology is selected for the loop filter for the following reasons: 1) it could reduce the number of required feedback DACs as much as possible; 2) it allows to implement the zero optimization for the TI DSM such that the performance could be further improved. Furthermore, we employ the technique of error correction to address the issue regarding the delay-free feedback path, which originates from the extrapolating TI DSM. We present the derivations of the target TI CT DSM starting from a single-channel discrete-time (DT) DSM, while the compensation for excess loop delay (ELD) is considered. Fabricated in 65nm CMOS process, this modulator achieves an equivalent output sampling rate of 800MS/s, while the analog channel operates at 400MHz. It exhibits a signal-to-noise and distortion ratio (SNDR) /spurious-free dynamic range (SFDR)/dynamic range (DR) of 75.5dB/89.7dB/79dB over a 10MHz bandwidth. The total power consumption is 33.73mW from 1.2v/1.8v power supplies. It results in a Schreier Figure of Merit (FoM) of 163.7dB based on DR.

This paper presents a continuous-time (CT) 0–4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0–4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0–4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR.

This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.

This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.

This paper presents a discrete-time multi-stage noise shaping (MASH) delta-sigma modulator (DSM) with second-order digital noise coupling for wideband highresolution applications. By directly injecting the output of the second loop into the quantizer input of the first loop while choosing an appropriate signal transfer function of the second loop, a second-order digital noise coupling can be easily constructed without almost imposing any hardware complexity. With the help of the second-order digital noise coupling, the inherent quantization noise leakage in the MASH topology is significantly mitigated, thus resulting in less DC gain requirement for the integrators. Mathematical analysis and further simulation results are presented to demonstrate the effectiveness of the proposed MASH structure.

This brief presents a time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an improved variance-based time-skew estimation technique, where we introduce a window detector (WD) based on a SAR ADC. It brings low hardware overhead and 104times faster convergence speed when compared to the prior variance-based time-skew calibration. Postlayout simulation results of a 10-bit, 2-GS/s TI-ADC in 28-nm CMOS process verify the effectiveness of the proposed calibration. The results indicate that the signal noise and distortion ratio/spurious free dynamic range of the ADC improved from 41.9/48.6 to 53.2/63.3 dB after calibration. The total area and power are 0.105 mm2and 14.9 mW, respectively, where the WD occupies 0.0015 mm2and 0.55 mW.

Nowadays, with global development in Internet of Things (IoTs), electricity, water, and gas information readings should be done in a convenient way. However, existing smart electric meters (SM) mainly focus on the information of financial transactions (the energy bill), whereas little effort has been done to promote the instrumentation dimension of the metering infrastructure. In this paper, we propose and develop a power quality indexes (PQIs) measurement system platform with remote alarm notification for electrical systems. Compared with the existing state-of-the-art, the proposed platform requires less development and maintenance cost, exhibiting higher flexibility. In this system we include the main power quality indexes, including root-mean-square (RMS) value, active power P, reactive power Q, apparent power S, power factor (PF), fundamental power factor (PF1) and total harmonic distortion (THD). To acquire those power quality indexes, we use a anticonjugate decomposition cascaded delayed signal cancellation (ACD-CDSC) technique. At last, we provide the experimental results of PQIs in a single-phase system to verify the effectiveness of the measurement platform with remote alarm notification in comparison with the Fluke power quality analyzer.

A 3-level boost (3LB) converter has the characteristics of higher voltage conversion efficiency, lower inductor current ripples, output voltage ripples and voltage stresses on switches when compared with the conventional boost converters in continuous conduction mode (CCM). When the 3LB is integrated on a chip, we cannot avoid its discontinuous conduction mode (DCM) operation due to a small inductance and load variation. In this paper we'll present and discuss the design and control of a 3LB converter in DCM operation, implemented in a 65-nm CMOS process. Transistor level simulation results show that it operates at 100 MHz with a 5nH inductor, a 4nF output capacitor and a 2.5nF fly capacitor achieving an output conversion range of 1.5 V to 2.1V from a 1.2 V input supply, with a peak efficiency of 83.2%@90mW, a load transient response of 141mV and 1.64ns/mA for undershoot, 136mV and 1.93ns/mA for overshoot, and a voltage ripple less than 60/85mV when ILoad =40/80mA with a typical and the maximum output voltage ripple of less than 90mV in the worst corner.

This paper presents the DC analysis of the Negative Output Elementary Luo Converter (NOELC), which includes the continuous-conduction mode (CCM) voltage gain and the boundary condition between the CCM and the discontinuous-conduction mode (DCM). The main features of the NOELC are the high gain with small ripple and the reverse output. Additionally, we address the parameters design of the NOELC and propose an output voltage ripple estimation method. Through MATLAB Simulink simulation, we further demonstrate that the parameters design and the output voltage estimation method can achieve more accurate results when compared with those from the conventional one.

This paper discusses the use of a low gain amplifier and a passive switched-capacitor (SC) network to enable the SC integrator function. The method is applied to a delta-sigma modulator to achieve high resolution as proved by the 65-nm CMOS technology test vehicle. Compared with the conventional operational amplifier (op-amp)-based SC integrator, this solution utilizes a low-gain open-loop amplifier to drive a passive SC integrator with positive feedback. Since the open-loop amplifier requires a low dc gain and implements an embedded current adder, the power consumption is very low. Power reduction for single bit is obtained by using passive feedforward with built-in adder to assist the first amplifier. The low swing obtained at the output of the active blocks relaxes the slew rate requirement and enhances the linearity. Implemented in 65-nm digital CMOS technology with an active area of 0.1 mm2, the test chip achieves a dynamic range of 91 dB, peak signal-to-noise ratio of 88.4 dB, peak signal-to-noise-plus-distortion ratio of 88.2 dB, and a spurious free dynamic range of 106 dB while consuming 73.6 μW in a 25-kHz signal bandwidth at 1 V supply, yielding a FoMWaldenof 70 fJ/conv-step and FoMSchreierof 176 dB.

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial Vcm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm2. The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.

This brief presents a uniform quantization theory (UQT)-based digital-to-analog converter (DAC) linearity calibration for a successive approximation register (SAR) analog-to-digital converter. According to the uniform quantization noise property, the nonlinearity due to the parasitics in an LSB array of the split-DAC structure is estimated and corrected in the digital domain. The calibration requires that the characteristic of the input signal must fulfill the prerogative of the quantization theory. The advantages lie in its low design complexity with no additional analog circuit modification. The proposed calibration is verified by both behavioral simulations and measured results in an SAR ADC. The measurements are based on a prototype implemented with large nonlinear split-DACs, which demonstrate that the UQT-based linearity calibration can effectively improve the Signal to Noise and Distortion (SNDR) from 56.9 to 63.3 dB at dc input with a sampling frequency of 120 MS/s.

A novel current mode Capacitor Based Sine-Shaped (CBSS) Digital-to-Analog Converter (DAC) for Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators, enabling smooth zero current transitions and greatly reducing the clock jitter noise, is described. The circuit is switched capacitor based and uses a cosine-wave voltage reference instead of constant current. The output is a sine-shaped waveform with precise zero transitions. Locking the reference cosine-wave voltage and the clock employed for data sampling ensures a virtual immunity to clock jitter. The use of a cosine-wave as reference and a constant capacitance loading the reference generator facilitates impedance matching thus making the scheme suitable for very high sampling rate. Moreover, the good matching between capacitors determines the accuracy of the integrators' time constant and multi-bit linearity of the proposed DAC. The feature of the method has been verified with behavioral simulations and tested in a second order ΣΔ modulator.

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

In this paper, a new VCO-assisted VCO-based sigma-delta (ΣΔ) modulator is proposed to improve the linearity of the VCO-based quantizer. The assistant network in the digital feedforward path reduces the input swing of the VCO-based quantizer in the main path, and then adds it together through the digital cancellation path to keep the same signal before and after quantization. Moreover, the merit of the auxiliary VCO increases the tolerance to DAC mismatches because of its intrinsic DEM function, which also simplifies the digital circuit part. A first order continuous-time (CT) ΣΔ modulator with the proposed structure is designed and simulated in a 65nm CMOS process. The performance of the modulator can reach 76.6dB/82.4dB SNDR/SNR with second order noise shaping and 84dB DR within a 10MHz bandwidth and a sampling frequency of 1.4GHz, consuming 9.4mW of power.

This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced VCM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and reference noise. The proposed 8-bit SAR ADC operates at 100MS/s with 0.6V supply in 65nm CMOS. The simulation results show that the design achieves 48.8dB SNDR with only 0.524mW power. The Figure-of-Merit (FoM) is 23.35fJ/conversion-step.

A novel structure of VCO-based quantizer for CT ΣΔ modulator is presented which can significantly improve the VCO linearity. Compared to the traditional methods, the proposed structure uses only one VCO in the system and it also maintains the intrinsic Dynamic Element Matching (DEM) function of the VCO-based quantizer. A first order CT ΣΔ modulator with the proposed quantizer is designed and simulated in a 65nm CMOS process. The DAC of the ΣΔ modulator is optimized, which can also save half of the DAC cells. The performance of the modulator can reach 69/67 dB SNR/SNDR and a dynamic range of 78 dB with a bandwidth of 10MHz at 1V supply voltage.

A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very low power dissipation. The technique is utilized in the design of a 10b 80MS/s SAR ADC in 65-nm CMOS technology. The simulation results show that the proposed charge compensation technique can improve the Effective Number of Bits (ENOB) from 8.3bits to 9.6bits and differential/integral nonlinearity from 3LSB/1.65LSB to 0.45LSB/0.74LSB respectively with only 300 uW power dissipation in the proposed charge compensation circuitry.

A power scalable 6-bit 1.2GS/s flash Analog-to-Digital Converter (ADC) is designed in 90nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is −0.9/+0.7 LSB and the INL is −0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pJ/conversion-step at Nyquist from 1.2V power supply.

A 1.056 GS/s, 5-bit/6-bit switchable flash analog-to-digital converter (ADC) is designed in 0.18-/spl mu/m CMOS, which is suitable to be used in an OFDM-UWB transceiver. A resolution switchable structure is proposed to optimize power consumption according to the dynamic requirement of the application. Two-stage interpolation and averaging techniques are employed to average the offset of the preamplifiers. Monte Carlo simulation results show that the proposed ADC achieves 4.2b/5.0b ENOB in 5-bit/6-bit working modes with a 413-MHz input signal. The mean value of DNL and INL is 0.32 and 0.56 LSB for 5-bit mode, while 0.47 and 0.62 LSB for 6-bit mode. The analog part consumes 36 mW and 98 mW from a 1.8-V supply in 5-bit and 6-bit operation mode, respectively.

Abstract- This paper proposes a novel finite-gain nonlinearity in MDACs of pipelined ADCs or poles and zeros compensation technique that can be applied to low-voltage deviations in SC filters or sigma-delta modulators, unless the high-speed reset- and switched-opamp circuits. The proposed produced finite-gain error can be compensated, with, for example, technique utilizes an Auxiliary Differential-Difference traditional Correlated Double Sampling (CDS) techniques [8,9]. Amplifier (A-DDA) that senses and corrects the finite-gain However this cannot be applied in a low-voltage environment due error from the virtual ground of the main opamp (with the to (a) limitations caused by the floating switch problems and (b) the effective gain in the order of jA2), thus allowing the use of fact that the opamp is switched off or reset in one clock phase, high-speed single-stage low-gain opamps (instead of usual low- which implies that it would not be idle and cannot be used to speed two-stage amplifier with large power consumption) to compensate the gain error. To overcome these drawbacks a low-achieve high-speed operation. Simulations of a reset-opamp 10- voltage finite-gain compensation technique can be used [4], but it bit 100 MHz pipelined ADC in 1.2-V supply voltage are has also a restriction of narrow-band operation (typically a bandpass presented using 0.18pm CMOS, with the Signal-to-Noise-and- sigma-delta modulator) that limits the signal band to be located only Distortion Ratio (SNDR) improved from 46.77 dB to 58.51 dB narrowly atf/4. and thus verifying the effectiveness of the proposed circuit. In this paper a novel low-voltage finite-gain-compensation technique is proposed. It utilizes an Auxiliary Differential-

Traditional jitter-noise analysis which mainly focuses on the clock jitter errors for impulse-sampled signals cannot accurately model the sampled-data systems that practically include nonuniform sample-and-hold effects. This paper presents a comprehensive and robust analysis of the imperfections of nonuniformly sampled-and-held signals due to clock jitter. Both the general signal to overall jitter noise ratio, and also the spurious free dynamic range subjected to narrow in-band noise tone are derived in closed-forms. Finally, a practical analysis of the timing-skew effects in designing a 21.4 MHz IF sampled-data filter for radio applications is addressed to illustrate the effectiveness of the derived formula.