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Simone Bettola

dblp:62/6461 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 62% Hardware accelerators and domain-specific architectures · 19% Integrated circuit design · 19%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator		 0.011998
High Performance Fault-Tolerant Digital Neural Networks · IEEE Trans. Computers 1998
Integrated circuit design › redundant number representation
redundant binary representation		 0.011998
High Performance Fault-Tolerant Digital Neural Networks · IEEE Trans. Computers 1998

Methods — techniques the papers use, named apart from their topics

three-rail logic · 0.0redundant binary representation · 0.0
YearPublicationVenuePosition
1998 High Performance Fault-Tolerant Digital Neural Networks
abstract
Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in the literature. This paper focuses both on data representation to support high-performance neural computation and on error detection to provide the basic information for fault tolerance by using the redundant binary representation with a three-rail logic implementation. Costs and performances are evaluated referring to multilayered feed-forward networks.
Simone Bettola, Vincenzo Piuri
 IEEE Trans. Computers1