This paper proposes a sample-and-hold amplifier (SHA)-less front-end stage structure suitable for pipeline ADCs in time-interleaving architecture with large interleaving factor. A low resolution SARADC is adopted as the sub-quantizer, and a bridge capacitor is introduced to connect the two capacitor arrays of the MDAC and the sub-ADC. Compared to commonly used pipelined-SAR ADC architectures, the proposed front-end stage structure reduces the reference load on the sub-quantizer during coarse conversion, while preserving the benefits of a shared sampling network in the sampling process. A 14-bit 500-MS/s pipeline ADC channel in an 8-way time-interleaved architecture utilizing the proposed front-end stage structure is designed in 28-nm CMOS process. Simulation results well demonstrate that the proposed front-end stage structure is highly immune to aperture errors, and shows the ADC channel achieves 69.13 dB SNDR and 83.8 dB SFDR at Nyquist frequency. With an estimated power consumption of 40-mW, a Walden FoM of 34.24-fJ/conv.-step is achieved.

This paper presents a PVT-robust, high gain range and high linearity analog baseband (ABB) circuit for wideband communication. The ABB circuit consists of a four-stage programmable gain amplifier (PGA) and an embedded second-order low pass filter (LPF). In order to satisfy the PVT variations, a novel PGA topology based on two-stage miller OTA with self PVT compensation and dynamic pole-capturing technique is proposed. Besides, the ABB circuit uses floating-bulk bias method to achieve high linearity. Fabricated in 28-nm CMOS process, the measurement results show that the ABB circuit can provide a programmable gain range from 0 to 40 dB with 6 dB coarse and 1 dB fine step, while the 3 dB bandwidth greater than 550 MHz. It obtains an OP1dBof 5dBm and OIP3 of 26.1dBm for the maximum gain state. The ABB circuit occupies a core area of 0.23 mm2and consumes a DC power consumption of 15 mW from 0.9-V supply.

This paper presents a high-speed, low-noise and low-offset dynamic latch comparator. In this work, a pair of auxiliary reset transistors is employed to increase the gain of the preamplifier while reducing the reset delay of the latch, which effectively improves the precision and speed of the comparator. The proposed comparator is controlled by two clocks, and the preamplifier is turned on before the regeneration phase to reduce the input-referred noise. In order to reduce power consumption and kickback noise, the preamplifier achieves dynamic operation by controlling a pair of cascode transistors while separating the regeneration node and the input pair. Otherwise, this work optimizes an efficient background calibration circuit to correct the offset. The proposed comparator has been designed and simulated in 12-nm FinFET CMOS technology. Simulation results show a delay of 20 ps at 10 mV input. The proposed comparator also achieves a 0.61 mV input-referred noise and an offset standard deviation of 1.9 mV.

This paper presents a fast dynamic biasing technique for push-pull input buffers in high-speed ADCs. It introduces a coupling capacitor to the gate of the buffer to pull down its overdrive voltage after sampling, thus turning it off in idle time. Due to the complementary structure, the kickback to the input from the gate of PMOS and NMOS can be canceled out, introducing no perturbation. The proposed technique is implemented and validated in a 28nm CMOS process with a push-pull source follower input buffer which works under a 1.2 V power supply with a bias current of 7.5mA on one side. The dynamic biasing circuit shuts down the single-ended current to 2mA after sampling, reducing the average current by 40% with 50% duty cycle.

This paper presents an 8-bit 1.6GS/s successive-approximation-register analog-to-digital converter (SAR ADC) with alternate comparators. To enhance dynamic performance and speed, a dither-based background relative offset calibration and a fast SAR logic are proposed. In the background calibration, the least significant bit (LSB) can indicate the polarity of the relative offset between comparators after injecting dither into the input, facilitating calibration without extra phase. The fast SAR logic, which includes a trigger logic and a digital-to-analog converter (DAC) control logic, features a 3-logic-gate delay, resulting in a reduced bit duration. These techniques are validated by a prototype 8-bit SAR ADC in 28 nm CMOS technology, exhibiting the highest speed (1.6 GS/s) and smallest area (0.0008 mm2) among single-channel 8-bit SAR ADC. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) improves from 31.6 dB to 43.6 dB, while the spurious-free dynamic range (SFDR) improves from 38.7 dB to 58.3 dB after offset calibration. It consumes 5.73 mW from 1-V supply, yielding a Walden FoM of 29.0 fJ/conv-step.

This work presents a reconfigurable continuous-time delta-sigma modulator (CTDSM) structure with hybrid loop filter using a time-interleaved successive approximation register (TI-SAR) as its quantizer for multi-mode application. Except the first OTA-based integrator, the rest part of the loop filter is put in the digital domain, including a 2rd-order digital integrator and a digital excess loop delay (ELD) compensation block, which can provide convenience for outstanding structure reconfiguration and compensation for ELD over one clock cycle. A cascade of integrators with feedback and feedforward (CIFB-F) structure with well controlled STF out-of-band peaking is also proposed at the price of a little more power than the cascade of integrators with feedforward (CIFF) structure. The oversampling ratio (OSR), bandwidth (BW), sampling frequency (fs) and even the structure can be easily configured to adapt for different application. A circuit-level simulation of a reconfigurable CTDSM modeled by Verilog-A is conducted, which reveals signal-to-quantization noise ratio (SQNR) > 78dB over a wide input signal BW (25MHz) under 1.2GHz sampling frequency.

This paper presents a floating-ring hybrid amplifier (FRHA) insensitive to PVT and common-mode variation, in which a floating power supply is used for the third stage. In differential-mode, the transistors of third stage are forced into the subthreshold region, which improves the loop gain and quickly realizes the pole separation, reducing the times of the oscillation convergence. As for common-mode, a pair of small cross-coupled NMOS is added as the load of first stage, which sharply reduced the common-mode gain without affecting the differential-mode gain much. Moreover, the floating power supply provided by the capacitor has natural common-mode stability. To achieve PVT robustness, a PVT tracking circuit for charging the power supply capacitor is designed, which solves the early shutdown of the third stage caused by insufficient capacitor charge at fast process corner and reduces oscillation cycles due to insufficient phase margin at slow process corner. This FRHA has been applied to a 12-bit 200MS/s pipelined-SAR ADC as residue amplifier (RA) in 65nm CMOS process. The simulation result achieves 67.95dB SNDR at Nyquist frequency and 1.2Vpeak-peak input, yielding a Walden FoM of 5.57 fJ/con-step.

This paper presents a high linearity front-end circuit for RF sampling ADCs, including an input buffer and a sampling network. The input buffer uses a two-stage NMOS cascode structure and is powered by a separate LDO to support a larger signal swing input with high power supply rejection (PSR) and linearity. We use bootstrap switch with bulk-switching techniques to ensure sampling linearity, while a feed-through compensation technique with self-cancellation of nonlinear junction capacitor is applied to achieve better performance at high-frequency inputs. The above techniques are validated at a 1GS/s ADC in 65nm process, and the simulation results show that the low-frequency PSR of the input buffer reaches over 120dB, and the SNR, SNDR and SFDR of the overall front-end circuit are 78.74dB, 72.37dB and 75.37dB at 2GHz frequency 1.6Vpp input. The −3dB bandwidth of the front-end circuit achieves 4.4GHz.

A Q-learning based current-steering digital to analog converter (DAC) calibration method is proposed in this paper for spurious-free dynamic range (SFDR) improvement. A look-up table (LUT) to control the switching sequence of the DAC elements is achieved by Q-learning for an optimal SFDR. Compared with the fixed element transition strategy proposed by manual derivation, the LUT can be updated by off-line training to deal with diverse and complex non-ideal factors limiting the SFDR of DAC. In this paper, a 2.0-GS/s 12-bit segmented current-steering DAC in 28nm process is simulated and the equivalent model is extracted to verify the effectiveness of the method. Simulation results show that, the SFDR over entire Nyquist bandwidth is larger than 70 dB with about 8 dB improvement using the proposed Q-learning method.

A split based all-digital background calibration for an 18-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The "split ADC" architecture is exploited to eliminate the signal interference and accelerate the convergence speed of the calibration. The output difference of two channels continuously drives the background calibration algorithm to estimate and correct the error caused by nonlinearities. To guarantee the validity of calibration with different inputs, shuffling scheme is adopted in capacitor array. Different dither signals are injected into two channels to achieve faster convergence, especially under the DC input. In the meanwhile, enough redundancy is introduced to capacitor array to avoid the decrease of input range caused by dither signal. A 4-bit coarse ADC is exploited to alleviate conversion time and provide dither injection. A behavior level model with various nonideal factors is established in MATLAB to prove the availability of calibration for an 18-bit pipelined-SAR ADC. The simulation shows that the ENOB achieves 16.5-bit, the SNDR is increased from 52.4 dB to 100.9 dB and the SFDR is improved from 72.3 dB to 119.6 dB.

A self-regulating negative charge pump using eight-phase clock for the input buffer application with a wide range of load current is presented in this paper. The eight-phase clock generated by delay-locked loop is adopted to reduce the area of the decoupling capacitance tremendously. Zero reversion loss cross-coupled topology is used to eliminate reversion loss, thus improving energy efficiency. Furthermore, the self-regulating system is proposed to adjust the driving capacity of the negative charge pump according to the load current of the input buffer, making the output of the charge pump stable for a wide range of load current. This design is implemented in 65nm CMOS process. According to the results, the decoupling capacitance can be reduced by 95.6%. The output voltage stays stable around -380mV with the load current from 40mA to 70mA.

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

A 12-bit 2-GS/s pipelined analog-to-digital converter (ADC) front-end stage in 28 nm process is presented. Sample-and-hold amplifier-less (SHA-less) structure is adopted to avoid additional noise, nonlinearity, and power. Aperture error tuning is presented to mitigate the inherited problem of the SHA-less structure. New split closed-loop multiplying digital-to-analog converter (MDAC) structure and 1.2 V dual- input amplifier is used to lower the power and to enhance the speed. Dithering is adopted and comparator threshold voltage dithering is modified for low supply voltage and higher speed. Simulation shows a 66.4 dB signal-to-noise-and-distortion ratio (SNDR) and 76.1 dB spurious-free dynamic range (SFDR) under 1.38 GHz input frequency. The wideband input range and the aperture error tunability are proven by the simulation. The 163.8 dB Schreier figure-of-merit (FoM) and 52.2 fJ/conv.-step Walden FoM is achieved based on an assumed 180 mW total power, of which 90 mW is consumed by the front-end stage.

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.

This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage. A dedicated path combining architecture is proposed for the flash sub-ADC-based pipeline ADC to reduce the aperture error, and expand the ADC input frequency up to 490 MHz under 200-Ms/s sampling rate. To further improve the accuracy and reduce power, the sampling capacitor splitting and comparator interpolation techniques are used in the first stage. The proposed ADC has been designed and fabricated in a 180-nm CMOS technology with an area of 2.43 mm2including ADC core, the biasing, and the calibration circuit. The measured signal to noise and distortion ratio (SNDR) is 70.6 and 65.6 dB for 30- and 385-MHz inputs, respectively. The SNDR remains 63.1 dB for 490-MHz input. The ADC core consumes 112-mW power under 1.8-V supply. The measured effective resolution bandwidth (ERBW) is about 250 MHz, and the Walden figure of merit (FoM) defined at the ERBW is 116 fJ/conversion-step.

A 14-bit 250MS/s low power pipeline analog-to-digital converter (ADC) implemented in a 0.18μιη CMOS process is presented in this paper. A SHA-less 3.5-bit front-end is adopted to achieve low power design. An aperture error eliminating technique and flash ADC optimization design techniques such as capacitor splitting, interpolation, and offset calibration, are both used to achieve wideband input even for the front-end with resolution up to 3.5-bit. The post simulation results show this ADC achieves an SNR of 74.6 dB, an SNDR of 74.4 dB and an SFDR of 87.1 dB with a 70MHz input signal, while maintaining an SNR > 72.5 dB and an SFDR > 77.4 dB up to 900MHz input signals. The ADC consumes 120mW from a 1.8 V supply.

This paper presents a low-power 2-channel 12-bit 2GS/S time-interleaved pipelined-SAR ADC in 28nm CMOS process. The design adopts SHA-less front-end, capacitor sharing between stages, current-reused and ping-pong operated MDAC amplifier, and hybrid reference buffer to reduce power consumption and optimize performance. Pre-layout simulation with noise shows that the proposed ADC achieves SNDR and SFDR of 64.1dB and 69.5dB respectively at Nyquist frequency. The effective resolution bandwidth is extended to 3.2GHz. The ADC consumes only 50mW, in which 30mW is dissipated by the wide-band input buffer. At Nyquist frequency, the proposed ADC achieves a Waiden FOM of 19fJ/conv.-step.

This paper presents a novel autocorrelation-based strategy for timing mismatch calibration in Time-Interleaved ADCs. Different from common technique, the proposed strategy doesn't let autocorrelation between each channel and the reference channel converge to the peak, but to one of the channels with a certain time interval away from the reference channel. It can accelerate convergence. The interval can be selected with much freedom and easily implemented. Representation of sub-ADC output can be only one-bit without a “dead zone”, thus it can further reduce hardware overhead. It's also independent from offset and gain calibration. Using the proposed strategy in a 2-channel 14-bit 500MS/s TIADC, simulation shows a convergence time of 192ms to 0.10/00Tsaccuracy under 212.4MHz input and initial 50/00Tstiming mismatch.

This paper presents an enhanced voltage reference for Switched-Capacitor ADCs. Charge losing effect is analyzed and quantized. Charge-Compensation-Based (CCB) technique is introduced to reduce the signal-dependent effect. Charge Compensation Unit (CCU) is designed to compensate charge. It features in low overhead on power and chip-size. A proof-of-principle CCB reference design for a 12-bit 500MS/s pipelined ADC is implemented. Simulation results show at least 3dB SNDR and 10dB SFDR improvement achieved, with input sweeping from low frequency to nyquist rate.

A digital background calibration algorithm is proposed to overcome nonlinearity caused by finite opamp gain and capacitor mismatch in pipelined analog-to-digital converter (ADC). The scheme, code frequency statistics (CFS), does not modify the classic pipelined stage, needs none of extra testing signals, and reduces the linearity requirement of the analog circuit. CFS is suitable for generic input and the cost of hardware is low. An experimental 14-bit pipelined ADC is fabricated to verify CFS. At 15MS/s, the measurement results show that INL errors drop from 90LSB to 0.8 LSB, SNDR grows from 38.6 dB to 66.7 dB, THD drops from -37.3dB to -82.8dB, and SFDR grows from 41.6 dBc to 86.1 dBc. The linearity of the pipelined ADC is improved significantly.

This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique is also used for the reduction of power and noise. The proposed stage relaxes the requirement for the gain of opamp by about 6dB comparing to the conventional one. For verification, a 14bit, 200MS/s pipelined ADC is designed in a 130nm CMOS process. The simulation results show 73.4 dB SNDR with noise and 88.8dBc SFDR at 95 MHz input frequency. The pipelined core power consumption is about 42mW at 1.2V supply, and the whole pipelined ADC has an energy efficiency of 178 fJ/conversion-step.

This paper presents a novel DC offset calibration method for the zero-IF (intermediate frequency) receiver that removes the PGA-gain-correlated offset residue. The conventional calibration method is usually based on the classic input/output referred offset model, in which the receiver IF programmable gain amplifiers (PGAs) have offset sources that varies a lot with different gain settings. Consequently, the conventional calibration method needs to generate the calibration code at each gain step and requires a huge look up table (LUT) to store the calibration values. This paper presents a new DC offset model which is gain non-correlated, by analyzing two types of commonly-used PGA. Based on the new model, a LUT-free single-step DC offset calibration method in together with the implementation circuit is designed. The proposed method has been verified on a practical zero-IF receiver circuit in a standard 0.18 μm CMOS technology through the Monte Carlo (MC) simulation. The simulation results show that the receiver IF output offset residue after calibration using the proposed method is reduced to below 12 mV, which is comparable to the LUT-based conventional calibration.

This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip's total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm2and is implemented in a 130nm CMOS process.

This paper provides an area-efficient, low power and high precision current-to-voltage integrator for photocurrent measuring by using correlated double sampling. A novel CDS scheme is devised by using an interstage capacitor instead of the large error store capacitor to reduce kT/C noise. An integrator prototype with the proposed technique is fabricated using 0.8-μm 2P2M CMOS process for demonstration. The measurement results show that the output noise is 95μV and 59μV with the integration capacitor 4pF and 32pF, respectively, both for a 33pF photodiode parasitic capacitor. For a 3V output swing at 5V supply, the resolution is about 15bit.

A robust passive UHF RFID backscatter system enhanced with spread spectrum technique is presented in this paper. Due to the weak signal energy of the backscatter chain, traditional RFID backscatter communication is easily affected by the noises, interferences, and interceptions from the environment. To solve the problem, spread spectrum technique is introduced into the backscatter link of RFID system. Simulated results show that this approach largely reduces the bit error rate and improves the system's reliability and security. For hardware realization, spectrum spreading operation is implemented in a RFID tag baseband processor, which is finally applied into a complete RFID tag and fabricated using 0.18 um 1P6M CMOS technology. Furthermore, de-spreading operation including the PN acquisition is integrated into a FPGA implementation of RFID reader. Thus, a complete robust RFID backscatter system enhanced with spread spectrum technique is constructed.

A capacitor switching technique for 1.5-bit/stage pipeline A/D converters is presented. This technique improves both integral nonlinearity (INL) and differential nonlinearity (DNL) performance due to capacitor mismatch. Monte Carlo simulation is carried out with all components' mismatches considered. The results show that the INL can be improved by 2.5 times and the DNL can be improved by 5 times. Comparing with the conventional capacitor mismatch calibration techniques, the proposed technique has the characteristics such as simple calibration circuits, undegraded conversion rate, and insensitive to the operation environment.

This paper presents an incomplete settling design technique for switched-capacitor pipelined analog-to-digital converters (ADCs) to improve conversion rate. An improved multiplying digital-to-analog converter (MDAC) is introduced to eliminate the memory effect between adjacent samples in the conventional MDAC with insufficient settling time. The repeatable interstage gain error and nonlinearity due to incomplete settling are then corrected by a digital background calibration scheme. Behavioral simulations of two 13-bit incomplete settling ADCs, one with the improved MDACs and the other with the conventional MDACs, are performed in MATLAB to verify the proposed technique. The simulation results show that, the first ADC has an almost undegraded dynamic performance until the settling time decreases to 30% of the complete settling time, and at the point of 30% complete settling time, the improvement of SNDR and SFDR over the second one is 36.2dB and 52.4dBc, respectively.