A low complexity slow frequency hopped wireless data communication system with rapid synchronization is proposed, designed, and implemented. Simulations to support the study of this approach has been conducted and reported. With only a knowledge of the set of hopping patterns, such an architecture can quickly collect the exact hopping pattern at the initial starting band to achieve reliable data communication in the sequel. Such an approach should be useful in many personal communication systems with mobile consumer electronics applications such as personal data assistants.>

A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.>

The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical fast Fourier transform (FFT) in terms of accuracy, complexity and speed. Theorems developed previously for the AFT algorithm are used to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A computationally balanced AFT algorithm for Fourier analysis and signal processing is developed. This algorithm does not require complex multiplications. A VLSI architecture is suggested for this amplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25% over that used by the direct method. This efficient AFT algorithm is shown to be identical to Brun's original AFT algorithm.>

An arithmetical approach to Fourier analysis, called the arithmetic Fourier transform (AFT), is developed for a two-dimensional (2D) signal. This 2D AFT algorithm is based on the arithmetical approach that H. Bruns originated in 1903. It uses alternating arithmetic averages of 2n samples over a period. The use of alternating arithmetic averages yields an algorithm of low complexity. The number of multiply operations, which compose a major part of the architecture, is reduced. This algorithm features parallel processing which can be effectively implemented with VLSI techniques or optical processors. As a consequence, it is expected that this arithmetic algorithm can compete in complexity and speed with the conventional 2D fast Fourier transform algorithm. Simulation of the algorithm for equally space 2D data is accomplished by using zero-order interpolation. Computer simulation demonstrates that the errors in the Fourier coefficients are tolerable for many applications.>

The authors describe the VLSI implementation of a general sidelobe cancellor (GSC) using powers-of-two arithmetic. The chip needed for this design carries six multiplications and seven additions. The layout of this chip is based on the standard cell and regular structure approach. To reduce the propagation delay of its carry-save addition unit, a fast ripple carry adder which has a single NAND gate delay for carry propagation is designed. This adder is designed to reduce the propagation delay of carries by a factor of two.>