A fast serial-parallel (FSP) multiplier design is derived from the carry-save add-shift (CSAS) multiplier structure. The CSAS technique accepts multiplier bits serially (lsb first) and produces outputs serially (lsb first). Multiplication of two n bit unsigned numbers requires 2n clock cycles to complete the process out of which n clocks are used for n-row carry-save additions, and the other n clocks are utilized only to propagate the remaining carries. This CSAS structure is modified so that it operates as a CSAS unit for the first n clocks and reconfigures itself as an n bit ripple-carry parallel adder at the (n + 1)st clock, thus allowing the carries to ripple through, eliminating the delay due to storage elements during the last n clocks. It is shown that this modification results in an about one-third increase in speed for an approximately one-third increase in hardware. The technique is extended to signed numbers represented in 2's complement form. Also, it is shown how these implementations can be modularized.

A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with only n adder modules. The technique is extended to two's complement number system. Also, a more complete picture of the actual implementation is depicted. Finally, we bring to the attention an already existing multiplier which fits into the bit-sequential multiplier category.