According to statistics the verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design process. This means that the verification process must be well structured and organized in order to efficiently reach desired verification goals. This paper describes the modelling of an exhaustive formal verification process of a digital IC with Workflow Petri Nets [8] and the WoPeD (Workflow Petri net Designer) tool [9], which supports modelling, simulation and analysis of a workflow process. The purpose of this work is to formalize and quantify the verification process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a verification process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.

Presents an evolving system for the analysis and visualization of parallel application performance on shared memory multiprocessors. Our system couples SimOS, a complete machine simulator, with Rivet, a powerful visualization environment. This system demonstrates how visualization is necessary to realize the full power of simulation for performance analysis. We identify several features required of the visualization system, including flexibility, exploratory interaction techniques and data aggregation schemes. We demonstrate the effectiveness of this parallel analysis and visualization system with a case study. We developed two visualizations within Rivet to study the Argus parallel rendering library, focusing on the memory system and process scheduling activity of Argus, respectively. Using these visualizations, we uncovered several unexpected interactions between Argus and the underlying operating system. The results of the analysis led to changes that greatly improved its performance and scalability. Argus had previously been unable to scale beyond 26 processors; after analysis and modification, it achieved linear speedup up to 45 processors.

The SUIF Explorer is an interactive parallelization tool that is more effective than previous systems in minimizing the number of lines of code that require programmer assistance. First, the interprocedural analyses in the SUIF system is successful in parallelizing many coarse-grain loops, thus minimizing the number of spurious dependences requiring attention. Second, the system uses dynamic execution analyzers to identify those important loops that are likely to be parallelizable. Third, the SUIF Explorer is the first to apply program slicing to aid programmers in interactive parallelization. The system guides the programmer in the parallelization process using a set of sophisticated visualization techniques.This paper demonstrates the effectiveness of the SUIF Explorer with three case studies. The programmer was able to speed up all three programs by examining only a small fraction of the program and privatizing a few variables.