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Dennis Finn

dblp:63/3704 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 58% Parallel and multicore computing · 19% Embedded and real-time systems · 12%

Topics — the 5 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
dataflow architecture
0.021985
A Distributed VLSI Architecture for Efficient Signal and Data Processing · IEEE Trans. Computers 1985
The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing · ISCA 1985
Parallel and multicore computing › multiprocessor system
dataflow multiprocessor
0.011985
The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing · ISCA 1985
Processor architecture and microarchitecture
multiprocessor architecture
0.011985
The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing · ISCA 1985
Hardware reliability and fault tolerance › fault-tolerant architecture
fault-tolerant multicomputer
0.011985
A Distributed VLSI Architecture for Efficient Signal and Data Processing · IEEE Trans. Computers 1985
Embedded and real-time systems
signal processing systems
0.011985
The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing · ISCA 1985

Methods — techniques the papers use, named apart from their topics

simulation · 0.0deterministic simulation · 0.0
YearPublicationVenuePosition
1985 The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing
abstract
The Hughes Data Flow Multiprocessor (HDFM) is a proposed high performance, fault tolerant, high level language programmable processor targeted for embedded signal and d•t• processing applications.Based on the data flow principle, the HDFM can exploit the inherent parallelism in applications without explicit programmer identification of independent tasks, thus freeing the programmer from the often difficult job of creating parallel tasks and assigning these to different processors.The d•t• flow architecture consists of many processing elements (PEs) connected by • three dimensional bussed-cube packet routing network.The PEs are designed for VLSI implementation to provide large throughput, real-time processing.The modular, extensible nature of the computer allows for • wide number of PEs to meet a range of throughput and reliability requirements.Simulation results have domonstrated high performance operation and high level language programmability.
Rex W. Vedder, Dennis Finn
ISCA2
1985 A Distributed VLSI Architecture for Efficient Signal and Data Processing
abstract
The machine described, the Hughes Data-Flow Multiprocessor (HDFM), is a high-performance, scalable, fault-tolerant, highly programmable multicomputer designed for embedded signal and data processing applications. The architecture of the machine is described in detail, and the influences on the final design of various requirements such as weight, size, power consumption, performance level and reliability are shown. The processing elements have been designed to reduce the number of VLSI component types required and for modularity of the physical system. The modular nature of the architecture allows a range of throughput and reliability requirements to be met. The model of execution, derived from original data-flow principles, is presented, as well as the various software tools which give the system its high-level language programmability. Complex constructs (such as large structure handling) are demonstrated. The results of a deterministic simulation of the machine show that a 64-processing-element machine may provide real throughput of 64 million instructions per second (MIPS).
Jean-Luc Gaudiot, Rex W. Vedder, George K. Tucker, Dennis Finn, Michael L. Campbell
IEEE Trans. Computers4