Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from VLDB 2026 / reviewers in the wild / expert

Lalgudi N. Kannan

dblp:63/4256 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis		 0.011994
A Methodology and Algorithms for Post-Placement Delay Optimization · DAC 1994
Electronic design automation
physical design		 0.011994
A Methodology and Algorithms for Post-Placement Delay Optimization · DAC 1994
Electronic design automation › physical design
placement		 0.011994
A Methodology and Algorithms for Post-Placement Delay Optimization · DAC 1994
Electronic design automation › logic synthesis › logic optimization
resynthesis		 0.011994
A Methodology and Algorithms for Post-Placement Delay Optimization · DAC 1994

Methods — techniques the papers use, named apart from their topics

placement-aware resynthesis · 0.0incremental netlist modification · 0.0
YearPublicationVenuePosition
1994 A Methodology and Algorithms for Post-Placement Delay Optimization
abstract
In this paper we present a placement-intelligent resynthesis methodology and optimization algorithms to meet post-layout timing constraints while at the same time reducing the interconnect congestion.We b egin with the synthesized design netlist after initial placement and make incremental modi cations { taking placement into account { to generate a nal netlist and placement that meets the delay constraints after place and route.The algorithms described have been implemented a s p art of a tool for placement based r esynthesis.The tool has been used with a number of pre-optimized designs from industry and to obtain improvements in post-placement delays ranging from 13 to 22% with improved r outability.
Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang
 DAC1