Demo Data from VLDB 2026 / reviewers in the wild / expert
Ramautar Sharma
dblp:63/4824
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Computer networks · 1 · 1 first-authorTheory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 49% Processor architecture and microarchitecture · 28% Integrated circuit design · 15% | |
| Computer graphics and multimedia
1 paper |
Audio and music processing · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Audio and music processing
speech synthesis |
0.0 | 1 | 1985 | Architecture Design of a High-Quality Speech Synthesizer Based on the Multipulse LPC Technique · IEEE J. Sel. Areas Commun. 1985 |
Processor architecture and microarchitecture › multiprocessor architecture
multiprocessor design |
0.0 | 1 | 1985 | Architecture Design of a High-Quality Speech Synthesizer Based on the Multipulse LPC Technique · IEEE J. Sel. Areas Commun. 1985 |
Electronic design automation › high-level synthesis
data path synthesis |
0.0 | 1 | 1984 | A technology independent MOS multiplier generator · DAC 1984 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1984 | A technology independent MOS multiplier generator · DAC 1984 |
Cloud and datacenter computing › resource provisioning
dynamic resource provisioning |
0.0 | 1 | 1985 | Architecture Design of a High-Quality Speech Synthesizer Based on the Multipulse LPC Technique · IEEE J. Sel. Areas Commun. 1985 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1984 | A technology independent MOS multiplier generator · DAC 1984 |
Integrated circuit design › digital circuit design
MOS circuits |
0.0 | 1 | 1984 | A technology independent MOS multiplier generator · DAC 1984 |
Methods — techniques the papers use, named apart from their topics
multipulse LPC · 0.0multiprocessor architecture · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | Area-time efficient arithmetic elements for VLSI systemsabstractAlgorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described. Ramautar Sharma |
IEEE Symposium on Computer Arithmetic | 1 |
| 1987 | An AND-OR Parallel Execution System for Logic Program Evaluation
Nam Sung Woo, Ramautar Sharma |
ICPP | 2 |
| 1985 | Architecture Design of a High-Quality Speech Synthesizer Based on the Multipulse LPC TechniqueabstractThis paper describes an architectural design of a high-quality speech synthesizer based on the multipulse linear predictive coding technique. The algorithms implemented in the design are derived. The main features of the synthesizer are a multiprocessor architecture, real time operation,\mu-/A-law coded PCM output, flexible system interface, relative ease of programming, high quality of synthesized speech, and variable bit rates. The synthesizer is highly testable as most of the internal resources can be addressed externally through a parallel system-controller port and a set of instructions. Ramautar Sharma |
IEEE J. Sel. Areas Commun. | 1 |
| 1984 | A technology independent MOS multiplier generator
Kung-Chao Chu, Ramautar Sharma |
DAC | 2 |